1 /* 2 * Copyright(c) 2016, Analogix Semiconductor. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #ifndef __ANX78xx_H 16 #define __ANX78xx_H 17 18 #define TX_P0 0x70 19 #define TX_P1 0x7a 20 #define TX_P2 0x72 21 22 #define RX_P0 0x7e 23 #define RX_P1 0x80 24 25 /***************************************************************/ 26 /* Register definition of device address 0x7e */ 27 /***************************************************************/ 28 29 /* 30 * System Control and Status 31 */ 32 33 /* Software Reset Register 1 */ 34 #define SP_SOFTWARE_RESET1_REG 0x11 35 #define SP_VIDEO_RST BIT(4) 36 #define SP_HDCP_MAN_RST BIT(2) 37 #define SP_TMDS_RST BIT(1) 38 #define SP_SW_MAN_RST BIT(0) 39 40 /* System Status Register */ 41 #define SP_SYSTEM_STATUS_REG 0x14 42 #define SP_TMDS_CLOCK_DET BIT(1) 43 #define SP_TMDS_DE_DET BIT(0) 44 45 /* HDMI Status Register */ 46 #define SP_HDMI_STATUS_REG 0x15 47 #define SP_HDMI_AUD_LAYOUT BIT(3) 48 #define SP_HDMI_DET BIT(0) 49 # define SP_DVI_MODE 0 50 # define SP_HDMI_MODE 1 51 52 /* HDMI Mute Control Register */ 53 #define SP_HDMI_MUTE_CTRL_REG 0x16 54 #define SP_AUD_MUTE BIT(1) 55 #define SP_VID_MUTE BIT(0) 56 57 /* System Power Down Register 1 */ 58 #define SP_SYSTEM_POWER_DOWN1_REG 0x18 59 #define SP_PWDN_CTRL BIT(0) 60 61 /* 62 * Audio and Video Auto Control 63 */ 64 65 /* Auto Audio and Video Control register */ 66 #define SP_AUDVID_CTRL_REG 0x20 67 #define SP_AVC_OE BIT(7) 68 #define SP_AAC_OE BIT(6) 69 #define SP_AVC_EN BIT(1) 70 #define SP_AAC_EN BIT(0) 71 72 /* Audio Exception Enable Registers */ 73 #define SP_AUD_EXCEPTION_ENABLE_BASE (0x24 - 1) 74 /* Bits for Audio Exception Enable Register 3 */ 75 #define SP_AEC_EN21 BIT(5) 76 77 /* 78 * Interrupt 79 */ 80 81 /* Interrupt Status Register 1 */ 82 #define SP_INT_STATUS1_REG 0x31 83 /* Bits for Interrupt Status Register 1 */ 84 #define SP_HDMI_DVI BIT(7) 85 #define SP_CKDT_CHG BIT(6) 86 #define SP_SCDT_CHG BIT(5) 87 #define SP_PCLK_CHG BIT(4) 88 #define SP_PLL_UNLOCK BIT(3) 89 #define SP_CABLE_PLUG_CHG BIT(2) 90 #define SP_SET_MUTE BIT(1) 91 #define SP_SW_INTR BIT(0) 92 /* Bits for Interrupt Status Register 2 */ 93 #define SP_HDCP_ERR BIT(5) 94 #define SP_AUDIO_SAMPLE_CHG BIT(0) /* undocumented */ 95 /* Bits for Interrupt Status Register 3 */ 96 #define SP_AUD_MODE_CHG BIT(0) 97 /* Bits for Interrupt Status Register 5 */ 98 #define SP_AUDIO_RCV BIT(0) 99 /* Bits for Interrupt Status Register 6 */ 100 #define SP_INT_STATUS6_REG 0x36 101 #define SP_CTS_RCV BIT(7) 102 #define SP_NEW_AUD_PKT BIT(4) 103 #define SP_NEW_AVI_PKT BIT(1) 104 #define SP_NEW_CP_PKT BIT(0) 105 /* Bits for Interrupt Status Register 7 */ 106 #define SP_NO_VSI BIT(7) 107 #define SP_NEW_VS BIT(4) 108 109 /* Interrupt Mask 1 Status Registers */ 110 #define SP_INT_MASK1_REG 0x41 111 112 /* HDMI US TIMER Control Register */ 113 #define SP_HDMI_US_TIMER_CTRL_REG 0x49 114 #define SP_MS_TIMER_MARGIN_10_8_MASK 0x07 115 116 /* 117 * TMDS Control 118 */ 119 120 /* TMDS Control Registers */ 121 #define SP_TMDS_CTRL_BASE (0x50 - 1) 122 /* Bits for TMDS Control Register 7 */ 123 #define SP_PD_RT BIT(0) 124 125 /* 126 * Video Control 127 */ 128 129 /* Video Status Register */ 130 #define SP_VIDEO_STATUS_REG 0x70 131 #define SP_COLOR_DEPTH_MASK 0xf0 132 #define SP_COLOR_DEPTH_SHIFT 4 133 # define SP_COLOR_DEPTH_MODE_LEGACY 0x00 134 # define SP_COLOR_DEPTH_MODE_24BIT 0x04 135 # define SP_COLOR_DEPTH_MODE_30BIT 0x05 136 # define SP_COLOR_DEPTH_MODE_36BIT 0x06 137 # define SP_COLOR_DEPTH_MODE_48BIT 0x07 138 139 /* Video Data Range Control Register */ 140 #define SP_VID_DATA_RANGE_CTRL_REG 0x83 141 #define SP_R2Y_INPUT_LIMIT BIT(1) 142 143 /* Pixel Clock High Resolution Counter Registers */ 144 #define SP_PCLK_HIGHRES_CNT_BASE (0x8c - 1) 145 146 /* 147 * Audio Control 148 */ 149 150 /* Number of Audio Channels Status Registers */ 151 #define SP_AUD_CH_STATUS_REG_NUM 6 152 153 /* Audio IN S/PDIF Channel Status Registers */ 154 #define SP_AUD_SPDIF_CH_STATUS_BASE 0xc7 155 156 /* Audio IN S/PDIF Channel Status Register 4 */ 157 #define SP_FS_FREQ_MASK 0x0f 158 # define SP_FS_FREQ_44100HZ 0x00 159 # define SP_FS_FREQ_48000HZ 0x02 160 # define SP_FS_FREQ_32000HZ 0x03 161 # define SP_FS_FREQ_88200HZ 0x08 162 # define SP_FS_FREQ_96000HZ 0x0a 163 # define SP_FS_FREQ_176400HZ 0x0c 164 # define SP_FS_FREQ_192000HZ 0x0e 165 166 /* 167 * Micellaneous Control Block 168 */ 169 170 /* CHIP Control Register */ 171 #define SP_CHIP_CTRL_REG 0xe3 172 #define SP_MAN_HDMI5V_DET BIT(3) 173 #define SP_PLLLOCK_CKDT_EN BIT(2) 174 #define SP_ANALOG_CKDT_EN BIT(1) 175 #define SP_DIGITAL_CKDT_EN BIT(0) 176 177 /* Packet Receiving Status Register */ 178 #define SP_PACKET_RECEIVING_STATUS_REG 0xf3 179 #define SP_AVI_RCVD BIT(5) 180 #define SP_VSI_RCVD BIT(1) 181 182 /***************************************************************/ 183 /* Register definition of device address 0x80 */ 184 /***************************************************************/ 185 186 /* HDCP BCAPS Shadow Register */ 187 #define SP_HDCP_BCAPS_SHADOW_REG 0x2a 188 #define SP_BCAPS_REPEATER BIT(5) 189 190 /* HDCP Status Register */ 191 #define SP_RX_HDCP_STATUS_REG 0x3f 192 #define SP_AUTH_EN BIT(4) 193 194 /* 195 * InfoFrame and Control Packet Registers 196 */ 197 198 /* AVI InfoFrame packet checksum */ 199 #define SP_AVI_INFOFRAME_CHECKSUM 0xa3 200 201 /* AVI InfoFrame Registers */ 202 #define SP_AVI_INFOFRAME_DATA_BASE 0xa4 203 204 #define SP_AVI_COLOR_F_MASK 0x60 205 #define SP_AVI_COLOR_F_SHIFT 5 206 207 /* Audio InfoFrame Registers */ 208 #define SP_AUD_INFOFRAME_DATA_BASE 0xc4 209 #define SP_AUD_INFOFRAME_LAYOUT_MASK 0x0f 210 211 /* MPEG/HDMI Vendor Specific InfoFrame Packet type code */ 212 #define SP_MPEG_VS_INFOFRAME_TYPE_REG 0xe0 213 214 /* MPEG/HDMI Vendor Specific InfoFrame Packet length */ 215 #define SP_MPEG_VS_INFOFRAME_LEN_REG 0xe2 216 217 /* MPEG/HDMI Vendor Specific InfoFrame Packet version number */ 218 #define SP_MPEG_VS_INFOFRAME_VER_REG 0xe1 219 220 /* MPEG/HDMI Vendor Specific InfoFrame Packet content */ 221 #define SP_MPEG_VS_INFOFRAME_DATA_BASE 0xe4 222 223 /* General Control Packet Register */ 224 #define SP_GENERAL_CTRL_PACKET_REG 0x9f 225 #define SP_CLEAR_AVMUTE BIT(4) 226 #define SP_SET_AVMUTE BIT(0) 227 228 /***************************************************************/ 229 /* Register definition of device address 0x70 */ 230 /***************************************************************/ 231 232 /* HDCP Status Register */ 233 #define SP_TX_HDCP_STATUS_REG 0x00 234 #define SP_AUTH_FAIL BIT(5) 235 #define SP_AUTHEN_PASS BIT(1) 236 237 /* HDCP Control Register 0 */ 238 #define SP_HDCP_CTRL0_REG 0x01 239 #define SP_RX_REPEATER BIT(6) 240 #define SP_RE_AUTH BIT(5) 241 #define SP_SW_AUTH_OK BIT(4) 242 #define SP_HARD_AUTH_EN BIT(3) 243 #define SP_HDCP_ENC_EN BIT(2) 244 #define SP_BKSV_SRM_PASS BIT(1) 245 #define SP_KSVLIST_VLD BIT(0) 246 /* HDCP Function Enabled */ 247 #define SP_HDCP_FUNCTION_ENABLED (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 248 249 /* HDCP Receiver BSTATUS Register 0 */ 250 #define SP_HDCP_RX_BSTATUS0_REG 0x1b 251 /* HDCP Receiver BSTATUS Register 1 */ 252 #define SP_HDCP_RX_BSTATUS1_REG 0x1c 253 254 /* HDCP Embedded "Blue Screen" Content Registers */ 255 #define SP_HDCP_VID0_BLUE_SCREEN_REG 0x2c 256 #define SP_HDCP_VID1_BLUE_SCREEN_REG 0x2d 257 #define SP_HDCP_VID2_BLUE_SCREEN_REG 0x2e 258 259 /* HDCP Wait R0 Timing Register */ 260 #define SP_HDCP_WAIT_R0_TIME_REG 0x40 261 262 /* HDCP Link Integrity Check Timer Register */ 263 #define SP_HDCP_LINK_CHECK_TIMER_REG 0x41 264 265 /* HDCP Repeater Ready Wait Timer Register */ 266 #define SP_HDCP_RPTR_RDY_WAIT_TIME_REG 0x42 267 268 /* HDCP Auto Timer Register */ 269 #define SP_HDCP_AUTO_TIMER_REG 0x51 270 271 /* HDCP Key Status Register */ 272 #define SP_HDCP_KEY_STATUS_REG 0x5e 273 274 /* HDCP Key Command Register */ 275 #define SP_HDCP_KEY_COMMAND_REG 0x5f 276 #define SP_DISABLE_SYNC_HDCP BIT(2) 277 278 /* OTP Memory Key Protection Registers */ 279 #define SP_OTP_KEY_PROTECT1_REG 0x60 280 #define SP_OTP_KEY_PROTECT2_REG 0x61 281 #define SP_OTP_KEY_PROTECT3_REG 0x62 282 #define SP_OTP_PSW1 0xa2 283 #define SP_OTP_PSW2 0x7e 284 #define SP_OTP_PSW3 0xc6 285 286 /* DP System Control Registers */ 287 #define SP_DP_SYSTEM_CTRL_BASE (0x80 - 1) 288 /* Bits for DP System Control Register 2 */ 289 #define SP_CHA_STA BIT(2) 290 /* Bits for DP System Control Register 3 */ 291 #define SP_HPD_STATUS BIT(6) 292 #define SP_STRM_VALID BIT(2) 293 /* Bits for DP System Control Register 4 */ 294 #define SP_ENHANCED_MODE BIT(3) 295 296 /* DP Video Control Register */ 297 #define SP_DP_VIDEO_CTRL_REG 0x84 298 #define SP_COLOR_F_MASK 0x06 299 #define SP_COLOR_F_SHIFT 1 300 #define SP_BPC_MASK 0xe0 301 #define SP_BPC_SHIFT 5 302 # define SP_BPC_6BITS 0x00 303 # define SP_BPC_8BITS 0x01 304 # define SP_BPC_10BITS 0x02 305 # define SP_BPC_12BITS 0x03 306 307 /* DP Audio Control Register */ 308 #define SP_DP_AUDIO_CTRL_REG 0x87 309 #define SP_AUD_EN BIT(0) 310 311 /* 10us Pulse Generate Timer Registers */ 312 #define SP_I2C_GEN_10US_TIMER0_REG 0x88 313 #define SP_I2C_GEN_10US_TIMER1_REG 0x89 314 315 /* Packet Send Control Register */ 316 #define SP_PACKET_SEND_CTRL_REG 0x90 317 #define SP_AUD_IF_UP BIT(7) 318 #define SP_AVI_IF_UD BIT(6) 319 #define SP_MPEG_IF_UD BIT(5) 320 #define SP_SPD_IF_UD BIT(4) 321 #define SP_AUD_IF_EN BIT(3) 322 #define SP_AVI_IF_EN BIT(2) 323 #define SP_MPEG_IF_EN BIT(1) 324 #define SP_SPD_IF_EN BIT(0) 325 326 /* DP HDCP Control Register */ 327 #define SP_DP_HDCP_CTRL_REG 0x92 328 #define SP_AUTO_EN BIT(7) 329 #define SP_AUTO_START BIT(5) 330 #define SP_LINK_POLLING BIT(1) 331 332 /* DP Main Link Bandwidth Setting Register */ 333 #define SP_DP_MAIN_LINK_BW_SET_REG 0xa0 334 #define SP_LINK_BW_SET_MASK 0x1f 335 #define SP_INITIAL_SLIM_M_AUD_SEL BIT(5) 336 337 /* DP Training Pattern Set Register */ 338 #define SP_DP_TRAINING_PATTERN_SET_REG 0xa2 339 340 /* DP Lane 0 Link Training Control Register */ 341 #define SP_DP_LANE0_LT_CTRL_REG 0xa3 342 #define SP_TX_SW_SET_MASK 0x1b 343 #define SP_MAX_PRE_REACH BIT(5) 344 #define SP_MAX_DRIVE_REACH BIT(4) 345 #define SP_PRE_EMP_LEVEL1 BIT(3) 346 #define SP_DRVIE_CURRENT_LEVEL1 BIT(0) 347 348 /* DP Link Training Control Register */ 349 #define SP_DP_LT_CTRL_REG 0xa8 350 #define SP_LT_ERROR_TYPE_MASK 0x70 351 # define SP_LT_NO_ERROR 0x00 352 # define SP_LT_AUX_WRITE_ERROR 0x01 353 # define SP_LT_MAX_DRIVE_REACHED 0x02 354 # define SP_LT_WRONG_LANE_COUNT_SET 0x03 355 # define SP_LT_LOOP_SAME_5_TIME 0x04 356 # define SP_LT_CR_FAIL_IN_EQ 0x05 357 # define SP_LT_EQ_LOOP_5_TIME 0x06 358 #define SP_LT_EN BIT(0) 359 360 /* DP CEP Training Control Registers */ 361 #define SP_DP_CEP_TRAINING_CTRL0_REG 0xa9 362 #define SP_DP_CEP_TRAINING_CTRL1_REG 0xaa 363 364 /* DP Debug Register 1 */ 365 #define SP_DP_DEBUG1_REG 0xb0 366 #define SP_DEBUG_PLL_LOCK BIT(4) 367 #define SP_POLLING_EN BIT(1) 368 369 /* DP Polling Control Register */ 370 #define SP_DP_POLLING_CTRL_REG 0xb4 371 #define SP_AUTO_POLLING_DISABLE BIT(0) 372 373 /* DP Link Debug Control Register */ 374 #define SP_DP_LINK_DEBUG_CTRL_REG 0xb8 375 #define SP_M_VID_DEBUG BIT(5) 376 #define SP_NEW_PRBS7 BIT(4) 377 #define SP_INSERT_ER BIT(1) 378 #define SP_PRBS31_EN BIT(0) 379 380 /* AUX Misc control Register */ 381 #define SP_AUX_MISC_CTRL_REG 0xbf 382 383 /* DP PLL control Register */ 384 #define SP_DP_PLL_CTRL_REG 0xc7 385 #define SP_PLL_RST BIT(6) 386 387 /* DP Analog Power Down Register */ 388 #define SP_DP_ANALOG_POWER_DOWN_REG 0xc8 389 #define SP_CH0_PD BIT(0) 390 391 /* DP Misc Control Register */ 392 #define SP_DP_MISC_CTRL_REG 0xcd 393 #define SP_EQ_TRAINING_LOOP BIT(6) 394 395 /* DP Extra I2C Device Address Register */ 396 #define SP_DP_EXTRA_I2C_DEV_ADDR_REG 0xce 397 #define SP_I2C_STRETCH_DISABLE BIT(7) 398 399 #define SP_I2C_EXTRA_ADDR 0x50 400 401 /* DP Downspread Control Register 1 */ 402 #define SP_DP_DOWNSPREAD_CTRL1_REG 0xd0 403 404 /* DP M Value Calculation Control Register */ 405 #define SP_DP_M_CALCULATION_CTRL_REG 0xd9 406 #define SP_M_GEN_CLK_SEL BIT(0) 407 408 /* AUX Channel Access Status Register */ 409 #define SP_AUX_CH_STATUS_REG 0xe0 410 #define SP_AUX_STATUS 0x0f 411 412 /* AUX Channel DEFER Control Register */ 413 #define SP_AUX_DEFER_CTRL_REG 0xe2 414 #define SP_DEFER_CTRL_EN BIT(7) 415 416 /* DP Buffer Data Count Register */ 417 #define SP_BUF_DATA_COUNT_REG 0xe4 418 #define SP_BUF_DATA_COUNT_MASK 0x1f 419 #define SP_BUF_CLR BIT(7) 420 421 /* DP AUX Channel Control Register 1 */ 422 #define SP_DP_AUX_CH_CTRL1_REG 0xe5 423 #define SP_AUX_TX_COMM_MASK 0x0f 424 #define SP_AUX_LENGTH_MASK 0xf0 425 #define SP_AUX_LENGTH_SHIFT 4 426 427 /* DP AUX CH Address Register 0 */ 428 #define SP_AUX_ADDR_7_0_REG 0xe6 429 430 /* DP AUX CH Address Register 1 */ 431 #define SP_AUX_ADDR_15_8_REG 0xe7 432 433 /* DP AUX CH Address Register 2 */ 434 #define SP_AUX_ADDR_19_16_REG 0xe8 435 #define SP_AUX_ADDR_19_16_MASK 0x0f 436 437 /* DP AUX Channel Control Register 2 */ 438 #define SP_DP_AUX_CH_CTRL2_REG 0xe9 439 #define SP_AUX_SEL_RXCM BIT(6) 440 #define SP_AUX_CHSEL BIT(3) 441 #define SP_AUX_PN_INV BIT(2) 442 #define SP_ADDR_ONLY BIT(1) 443 #define SP_AUX_EN BIT(0) 444 445 /* DP Video Stream Control InfoFrame Register */ 446 #define SP_DP_3D_VSC_CTRL_REG 0xea 447 #define SP_INFO_FRAME_VSC_EN BIT(0) 448 449 /* DP Video Stream Data Byte 1 Register */ 450 #define SP_DP_VSC_DB1_REG 0xeb 451 452 /* DP AUX Channel Control Register 3 */ 453 #define SP_DP_AUX_CH_CTRL3_REG 0xec 454 #define SP_WAIT_COUNTER_7_0_MASK 0xff 455 456 /* DP AUX Channel Control Register 4 */ 457 #define SP_DP_AUX_CH_CTRL4_REG 0xed 458 459 /* DP AUX Buffer Data Registers */ 460 #define SP_DP_BUF_DATA0_REG 0xf0 461 462 /***************************************************************/ 463 /* Register definition of device address 0x72 */ 464 /***************************************************************/ 465 466 /* 467 * Core Register Definitions 468 */ 469 470 /* Device ID Low Byte Register */ 471 #define SP_DEVICE_IDL_REG 0x02 472 473 /* Device ID High Byte Register */ 474 #define SP_DEVICE_IDH_REG 0x03 475 476 /* Device version register */ 477 #define SP_DEVICE_VERSION_REG 0x04 478 479 /* Power Down Control Register */ 480 #define SP_POWERDOWN_CTRL_REG 0x05 481 #define SP_REGISTER_PD BIT(7) 482 #define SP_HDCP_PD BIT(5) 483 #define SP_AUDIO_PD BIT(4) 484 #define SP_VIDEO_PD BIT(3) 485 #define SP_LINK_PD BIT(2) 486 #define SP_TOTAL_PD BIT(1) 487 488 /* Reset Control Register 1 */ 489 #define SP_RESET_CTRL1_REG 0x06 490 #define SP_MISC_RST BIT(7) 491 #define SP_VIDCAP_RST BIT(6) 492 #define SP_VIDFIF_RST BIT(5) 493 #define SP_AUDFIF_RST BIT(4) 494 #define SP_AUDCAP_RST BIT(3) 495 #define SP_HDCP_RST BIT(2) 496 #define SP_SW_RST BIT(1) 497 #define SP_HW_RST BIT(0) 498 499 /* Reset Control Register 2 */ 500 #define SP_RESET_CTRL2_REG 0x07 501 #define SP_AUX_RST BIT(2) 502 #define SP_SERDES_FIFO_RST BIT(1) 503 #define SP_I2C_REG_RST BIT(0) 504 505 /* Video Control Register 1 */ 506 #define SP_VID_CTRL1_REG 0x08 507 #define SP_VIDEO_EN BIT(7) 508 #define SP_VIDEO_MUTE BIT(2) 509 #define SP_DE_GEN BIT(1) 510 #define SP_DEMUX BIT(0) 511 512 /* Video Control Register 2 */ 513 #define SP_VID_CTRL2_REG 0x09 514 #define SP_IN_COLOR_F_MASK 0x03 515 #define SP_IN_YC_BIT_SEL BIT(2) 516 #define SP_IN_BPC_MASK 0x70 517 #define SP_IN_BPC_SHIFT 4 518 # define SP_IN_BPC_12BIT 0x03 519 # define SP_IN_BPC_10BIT 0x02 520 # define SP_IN_BPC_8BIT 0x01 521 # define SP_IN_BPC_6BIT 0x00 522 #define SP_IN_D_RANGE BIT(7) 523 524 /* Video Control Register 3 */ 525 #define SP_VID_CTRL3_REG 0x0a 526 #define SP_HPD_OUT BIT(6) 527 528 /* Video Control Register 5 */ 529 #define SP_VID_CTRL5_REG 0x0c 530 #define SP_CSC_STD_SEL BIT(7) 531 #define SP_XVYCC_RNG_LMT BIT(6) 532 #define SP_RANGE_Y2R BIT(5) 533 #define SP_CSPACE_Y2R BIT(4) 534 #define SP_RGB_RNG_LMT BIT(3) 535 #define SP_Y_RNG_LMT BIT(2) 536 #define SP_RANGE_R2Y BIT(1) 537 #define SP_CSPACE_R2Y BIT(0) 538 539 /* Video Control Register 6 */ 540 #define SP_VID_CTRL6_REG 0x0d 541 #define SP_TEST_PATTERN_EN BIT(7) 542 #define SP_VIDEO_PROCESS_EN BIT(6) 543 #define SP_VID_US_MODE BIT(3) 544 #define SP_VID_DS_MODE BIT(2) 545 #define SP_UP_SAMPLE BIT(1) 546 #define SP_DOWN_SAMPLE BIT(0) 547 548 /* Video Control Register 8 */ 549 #define SP_VID_CTRL8_REG 0x0f 550 #define SP_VID_VRES_TH BIT(0) 551 552 /* Total Line Status Low Byte Register */ 553 #define SP_TOTAL_LINE_STAL_REG 0x24 554 555 /* Total Line Status High Byte Register */ 556 #define SP_TOTAL_LINE_STAH_REG 0x25 557 558 /* Active Line Status Low Byte Register */ 559 #define SP_ACT_LINE_STAL_REG 0x26 560 561 /* Active Line Status High Byte Register */ 562 #define SP_ACT_LINE_STAH_REG 0x27 563 564 /* Vertical Front Porch Status Register */ 565 #define SP_V_F_PORCH_STA_REG 0x28 566 567 /* Vertical SYNC Width Status Register */ 568 #define SP_V_SYNC_STA_REG 0x29 569 570 /* Vertical Back Porch Status Register */ 571 #define SP_V_B_PORCH_STA_REG 0x2a 572 573 /* Total Pixel Status Low Byte Register */ 574 #define SP_TOTAL_PIXEL_STAL_REG 0x2b 575 576 /* Total Pixel Status High Byte Register */ 577 #define SP_TOTAL_PIXEL_STAH_REG 0x2c 578 579 /* Active Pixel Status Low Byte Register */ 580 #define SP_ACT_PIXEL_STAL_REG 0x2d 581 582 /* Active Pixel Status High Byte Register */ 583 #define SP_ACT_PIXEL_STAH_REG 0x2e 584 585 /* Horizontal Front Porch Status Low Byte Register */ 586 #define SP_H_F_PORCH_STAL_REG 0x2f 587 588 /* Horizontal Front Porch Statys High Byte Register */ 589 #define SP_H_F_PORCH_STAH_REG 0x30 590 591 /* Horizontal SYNC Width Status Low Byte Register */ 592 #define SP_H_SYNC_STAL_REG 0x31 593 594 /* Horizontal SYNC Width Status High Byte Register */ 595 #define SP_H_SYNC_STAH_REG 0x32 596 597 /* Horizontal Back Porch Status Low Byte Register */ 598 #define SP_H_B_PORCH_STAL_REG 0x33 599 600 /* Horizontal Back Porch Status High Byte Register */ 601 #define SP_H_B_PORCH_STAH_REG 0x34 602 603 /* InfoFrame AVI Packet DB1 Register */ 604 #define SP_INFOFRAME_AVI_DB1_REG 0x70 605 606 /* Bit Control Specific Register */ 607 #define SP_BIT_CTRL_SPECIFIC_REG 0x80 608 #define SP_BIT_CTRL_SELECT_SHIFT 1 609 #define SP_ENABLE_BIT_CTRL BIT(0) 610 611 /* InfoFrame Audio Packet DB1 Register */ 612 #define SP_INFOFRAME_AUD_DB1_REG 0x83 613 614 /* InfoFrame MPEG Packet DB1 Register */ 615 #define SP_INFOFRAME_MPEG_DB1_REG 0xb0 616 617 /* Audio Channel Status Registers */ 618 #define SP_AUD_CH_STATUS_BASE 0xd0 619 620 /* Audio Channel Num Register 5 */ 621 #define SP_I2S_CHANNEL_NUM_MASK 0xe0 622 # define SP_I2S_CH_NUM_1 (0x00 << 5) 623 # define SP_I2S_CH_NUM_2 (0x01 << 5) 624 # define SP_I2S_CH_NUM_3 (0x02 << 5) 625 # define SP_I2S_CH_NUM_4 (0x03 << 5) 626 # define SP_I2S_CH_NUM_5 (0x04 << 5) 627 # define SP_I2S_CH_NUM_6 (0x05 << 5) 628 # define SP_I2S_CH_NUM_7 (0x06 << 5) 629 # define SP_I2S_CH_NUM_8 (0x07 << 5) 630 #define SP_EXT_VUCP BIT(2) 631 #define SP_VBIT BIT(1) 632 #define SP_AUDIO_LAYOUT BIT(0) 633 634 /* Analog Debug Register 2 */ 635 #define SP_ANALOG_DEBUG2_REG 0xdd 636 #define SP_FORCE_SW_OFF_BYPASS 0x20 637 #define SP_XTAL_FRQ 0x1c 638 # define SP_XTAL_FRQ_19M2 (0x00 << 2) 639 # define SP_XTAL_FRQ_24M (0x01 << 2) 640 # define SP_XTAL_FRQ_25M (0x02 << 2) 641 # define SP_XTAL_FRQ_26M (0x03 << 2) 642 # define SP_XTAL_FRQ_27M (0x04 << 2) 643 # define SP_XTAL_FRQ_38M4 (0x05 << 2) 644 # define SP_XTAL_FRQ_52M (0x06 << 2) 645 #define SP_POWERON_TIME_1P5MS 0x03 646 647 /* Analog Control 0 Register */ 648 #define SP_ANALOG_CTRL0_REG 0xe1 649 650 /* Common Interrupt Status Register 1 */ 651 #define SP_COMMON_INT_STATUS_BASE (0xf1 - 1) 652 #define SP_PLL_LOCK_CHG 0x40 653 654 /* Common Interrupt Status Register 2 */ 655 #define SP_COMMON_INT_STATUS2 0xf2 656 #define SP_HDCP_AUTH_CHG BIT(1) 657 #define SP_HDCP_AUTH_DONE BIT(0) 658 659 #define SP_HDCP_LINK_CHECK_FAIL BIT(0) 660 661 /* Common Interrupt Status Register 4 */ 662 #define SP_COMMON_INT_STATUS4_REG 0xf4 663 #define SP_HPD_IRQ BIT(6) 664 #define SP_HPD_ESYNC_ERR BIT(4) 665 #define SP_HPD_CHG BIT(2) 666 #define SP_HPD_LOST BIT(1) 667 #define SP_HPD_PLUG BIT(0) 668 669 /* DP Interrupt Status Register */ 670 #define SP_DP_INT_STATUS1_REG 0xf7 671 #define SP_TRAINING_FINISH BIT(5) 672 #define SP_POLLING_ERR BIT(4) 673 674 /* Common Interrupt Mask Register */ 675 #define SP_COMMON_INT_MASK_BASE (0xf8 - 1) 676 677 #define SP_COMMON_INT_MASK4_REG 0xfb 678 679 /* DP Interrupts Mask Register */ 680 #define SP_DP_INT_MASK1_REG 0xfe 681 682 /* Interrupt Control Register */ 683 #define SP_INT_CTRL_REG 0xff 684 685 /***************************************************************/ 686 /* Register definition of device address 0x7a */ 687 /***************************************************************/ 688 689 /* DP TX Link Training Control Register */ 690 #define SP_DP_TX_LT_CTRL0_REG 0x30 691 692 /* PD 1.2 Lint Training 80bit Pattern Register */ 693 #define SP_DP_LT_80BIT_PATTERN0_REG 0x80 694 #define SP_DP_LT_80BIT_PATTERN_REG_NUM 10 695 696 /* Audio Interface Control Register 0 */ 697 #define SP_AUD_INTERFACE_CTRL0_REG 0x5f 698 #define SP_AUD_INTERFACE_DISABLE 0x80 699 700 /* Audio Interface Control Register 2 */ 701 #define SP_AUD_INTERFACE_CTRL2_REG 0x60 702 #define SP_M_AUD_ADJUST_ST 0x04 703 704 /* Audio Interface Control Register 3 */ 705 #define SP_AUD_INTERFACE_CTRL3_REG 0x62 706 707 /* Audio Interface Control Register 4 */ 708 #define SP_AUD_INTERFACE_CTRL4_REG 0x67 709 710 /* Audio Interface Control Register 5 */ 711 #define SP_AUD_INTERFACE_CTRL5_REG 0x68 712 713 /* Audio Interface Control Register 6 */ 714 #define SP_AUD_INTERFACE_CTRL6_REG 0x69 715 716 /* Firmware Version Register */ 717 #define SP_FW_VER_REG 0xb7 718 719 #endif 720