1 /*
2 * i.MX drm driver - Television Encoder (TVEv2)
3 *
4 * Copyright (C) 2013 Philipp Zabel, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/clk.h>
17 #include <linux/clk-provider.h>
18 #include <linux/component.h>
19 #include <linux/module.h>
20 #include <linux/i2c.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/spinlock.h>
24 #include <linux/videodev2.h>
25 #include <drm/drmP.h>
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/drm_fb_helper.h>
28 #include <drm/drm_crtc_helper.h>
29 #include <video/imx-ipu-v3.h>
30
31 #include "imx-drm.h"
32
33 #define TVE_COM_CONF_REG 0x00
34 #define TVE_TVDAC0_CONT_REG 0x28
35 #define TVE_TVDAC1_CONT_REG 0x2c
36 #define TVE_TVDAC2_CONT_REG 0x30
37 #define TVE_CD_CONT_REG 0x34
38 #define TVE_INT_CONT_REG 0x64
39 #define TVE_STAT_REG 0x68
40 #define TVE_TST_MODE_REG 0x6c
41 #define TVE_MV_CONT_REG 0xdc
42
43 /* TVE_COM_CONF_REG */
44 #define TVE_SYNC_CH_2_EN BIT(22)
45 #define TVE_SYNC_CH_1_EN BIT(21)
46 #define TVE_SYNC_CH_0_EN BIT(20)
47 #define TVE_TV_OUT_MODE_MASK (0x7 << 12)
48 #define TVE_TV_OUT_DISABLE (0x0 << 12)
49 #define TVE_TV_OUT_CVBS_0 (0x1 << 12)
50 #define TVE_TV_OUT_CVBS_2 (0x2 << 12)
51 #define TVE_TV_OUT_CVBS_0_2 (0x3 << 12)
52 #define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12)
53 #define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12)
54 #define TVE_TV_OUT_YPBPR (0x6 << 12)
55 #define TVE_TV_OUT_RGB (0x7 << 12)
56 #define TVE_TV_STAND_MASK (0xf << 8)
57 #define TVE_TV_STAND_HD_1080P30 (0xc << 8)
58 #define TVE_P2I_CONV_EN BIT(7)
59 #define TVE_INP_VIDEO_FORM BIT(6)
60 #define TVE_INP_YCBCR_422 (0x0 << 6)
61 #define TVE_INP_YCBCR_444 (0x1 << 6)
62 #define TVE_DATA_SOURCE_MASK (0x3 << 4)
63 #define TVE_DATA_SOURCE_BUS1 (0x0 << 4)
64 #define TVE_DATA_SOURCE_BUS2 (0x1 << 4)
65 #define TVE_DATA_SOURCE_EXT (0x2 << 4)
66 #define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
67 #define TVE_IPU_CLK_EN_OFS 3
68 #define TVE_IPU_CLK_EN BIT(3)
69 #define TVE_DAC_SAMP_RATE_OFS 1
70 #define TVE_DAC_SAMP_RATE_WIDTH 2
71 #define TVE_DAC_SAMP_RATE_MASK (0x3 << 1)
72 #define TVE_DAC_FULL_RATE (0x0 << 1)
73 #define TVE_DAC_DIV2_RATE (0x1 << 1)
74 #define TVE_DAC_DIV4_RATE (0x2 << 1)
75 #define TVE_EN BIT(0)
76
77 /* TVE_TVDACx_CONT_REG */
78 #define TVE_TVDAC_GAIN_MASK (0x3f << 0)
79
80 /* TVE_CD_CONT_REG */
81 #define TVE_CD_CH_2_SM_EN BIT(22)
82 #define TVE_CD_CH_1_SM_EN BIT(21)
83 #define TVE_CD_CH_0_SM_EN BIT(20)
84 #define TVE_CD_CH_2_LM_EN BIT(18)
85 #define TVE_CD_CH_1_LM_EN BIT(17)
86 #define TVE_CD_CH_0_LM_EN BIT(16)
87 #define TVE_CD_CH_2_REF_LVL BIT(10)
88 #define TVE_CD_CH_1_REF_LVL BIT(9)
89 #define TVE_CD_CH_0_REF_LVL BIT(8)
90 #define TVE_CD_EN BIT(0)
91
92 /* TVE_INT_CONT_REG */
93 #define TVE_FRAME_END_IEN BIT(13)
94 #define TVE_CD_MON_END_IEN BIT(2)
95 #define TVE_CD_SM_IEN BIT(1)
96 #define TVE_CD_LM_IEN BIT(0)
97
98 /* TVE_TST_MODE_REG */
99 #define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0)
100
101 #define IMX_TVE_DAC_VOLTAGE 2750000
102
103 enum {
104 TVE_MODE_TVOUT,
105 TVE_MODE_VGA,
106 };
107
108 struct imx_tve {
109 struct drm_connector connector;
110 struct drm_encoder encoder;
111 struct device *dev;
112 spinlock_t lock; /* register lock */
113 bool enabled;
114 int mode;
115 int di_hsync_pin;
116 int di_vsync_pin;
117
118 struct regmap *regmap;
119 struct regulator *dac_reg;
120 struct i2c_adapter *ddc;
121 struct clk *clk;
122 struct clk *di_sel_clk;
123 struct clk_hw clk_hw_di;
124 struct clk *di_clk;
125 };
126
con_to_tve(struct drm_connector * c)127 static inline struct imx_tve *con_to_tve(struct drm_connector *c)
128 {
129 return container_of(c, struct imx_tve, connector);
130 }
131
enc_to_tve(struct drm_encoder * e)132 static inline struct imx_tve *enc_to_tve(struct drm_encoder *e)
133 {
134 return container_of(e, struct imx_tve, encoder);
135 }
136
tve_lock(void * __tve)137 static void tve_lock(void *__tve)
138 __acquires(&tve->lock)
139 {
140 struct imx_tve *tve = __tve;
141
142 spin_lock(&tve->lock);
143 }
144
tve_unlock(void * __tve)145 static void tve_unlock(void *__tve)
146 __releases(&tve->lock)
147 {
148 struct imx_tve *tve = __tve;
149
150 spin_unlock(&tve->lock);
151 }
152
tve_enable(struct imx_tve * tve)153 static void tve_enable(struct imx_tve *tve)
154 {
155 int ret;
156
157 if (!tve->enabled) {
158 tve->enabled = true;
159 clk_prepare_enable(tve->clk);
160 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
161 TVE_EN, TVE_EN);
162 }
163
164 /* clear interrupt status register */
165 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
166
167 /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
168 if (tve->mode == TVE_MODE_VGA)
169 regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
170 else
171 regmap_write(tve->regmap, TVE_INT_CONT_REG,
172 TVE_CD_SM_IEN |
173 TVE_CD_LM_IEN |
174 TVE_CD_MON_END_IEN);
175 }
176
tve_disable(struct imx_tve * tve)177 static void tve_disable(struct imx_tve *tve)
178 {
179 int ret;
180
181 if (tve->enabled) {
182 tve->enabled = false;
183 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
184 TVE_EN, 0);
185 clk_disable_unprepare(tve->clk);
186 }
187 }
188
tve_setup_tvout(struct imx_tve * tve)189 static int tve_setup_tvout(struct imx_tve *tve)
190 {
191 return -ENOTSUPP;
192 }
193
tve_setup_vga(struct imx_tve * tve)194 static int tve_setup_vga(struct imx_tve *tve)
195 {
196 unsigned int mask;
197 unsigned int val;
198 int ret;
199
200 /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
201 ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
202 TVE_TVDAC_GAIN_MASK, 0x0a);
203 if (ret)
204 return ret;
205
206 ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
207 TVE_TVDAC_GAIN_MASK, 0x0a);
208 if (ret)
209 return ret;
210
211 ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
212 TVE_TVDAC_GAIN_MASK, 0x0a);
213 if (ret)
214 return ret;
215
216 /* set configuration register */
217 mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
218 val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
219 mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN;
220 val |= TVE_TV_STAND_HD_1080P30 | 0;
221 mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
222 val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN;
223 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
224 if (ret)
225 return ret;
226
227 /* set test mode (as documented) */
228 return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
229 TVE_TVDAC_TEST_MODE_MASK, 1);
230 }
231
imx_tve_connector_detect(struct drm_connector * connector,bool force)232 static enum drm_connector_status imx_tve_connector_detect(
233 struct drm_connector *connector, bool force)
234 {
235 return connector_status_connected;
236 }
237
imx_tve_connector_get_modes(struct drm_connector * connector)238 static int imx_tve_connector_get_modes(struct drm_connector *connector)
239 {
240 struct imx_tve *tve = con_to_tve(connector);
241 struct edid *edid;
242 int ret = 0;
243
244 if (!tve->ddc)
245 return 0;
246
247 edid = drm_get_edid(connector, tve->ddc);
248 if (edid) {
249 drm_mode_connector_update_edid_property(connector, edid);
250 ret = drm_add_edid_modes(connector, edid);
251 kfree(edid);
252 }
253
254 return ret;
255 }
256
imx_tve_connector_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)257 static int imx_tve_connector_mode_valid(struct drm_connector *connector,
258 struct drm_display_mode *mode)
259 {
260 struct imx_tve *tve = con_to_tve(connector);
261 unsigned long rate;
262
263 /* pixel clock with 2x oversampling */
264 rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
265 if (rate == mode->clock)
266 return MODE_OK;
267
268 /* pixel clock without oversampling */
269 rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
270 if (rate == mode->clock)
271 return MODE_OK;
272
273 dev_warn(tve->dev, "ignoring mode %dx%d\n",
274 mode->hdisplay, mode->vdisplay);
275
276 return MODE_BAD;
277 }
278
imx_tve_connector_best_encoder(struct drm_connector * connector)279 static struct drm_encoder *imx_tve_connector_best_encoder(
280 struct drm_connector *connector)
281 {
282 struct imx_tve *tve = con_to_tve(connector);
283
284 return &tve->encoder;
285 }
286
imx_tve_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * orig_mode,struct drm_display_mode * mode)287 static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
288 struct drm_display_mode *orig_mode,
289 struct drm_display_mode *mode)
290 {
291 struct imx_tve *tve = enc_to_tve(encoder);
292 unsigned long rounded_rate;
293 unsigned long rate;
294 int div = 1;
295 int ret;
296
297 /*
298 * FIXME
299 * we should try 4k * mode->clock first,
300 * and enable 4x oversampling for lower resolutions
301 */
302 rate = 2000UL * mode->clock;
303 clk_set_rate(tve->clk, rate);
304 rounded_rate = clk_get_rate(tve->clk);
305 if (rounded_rate >= rate)
306 div = 2;
307 clk_set_rate(tve->di_clk, rounded_rate / div);
308
309 ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
310 if (ret < 0) {
311 dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
312 ret);
313 }
314
315 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
316 TVE_IPU_CLK_EN, TVE_IPU_CLK_EN);
317
318 if (tve->mode == TVE_MODE_VGA)
319 ret = tve_setup_vga(tve);
320 else
321 ret = tve_setup_tvout(tve);
322 if (ret)
323 dev_err(tve->dev, "failed to set configuration: %d\n", ret);
324 }
325
imx_tve_encoder_enable(struct drm_encoder * encoder)326 static void imx_tve_encoder_enable(struct drm_encoder *encoder)
327 {
328 struct imx_tve *tve = enc_to_tve(encoder);
329
330 tve_enable(tve);
331 }
332
imx_tve_encoder_disable(struct drm_encoder * encoder)333 static void imx_tve_encoder_disable(struct drm_encoder *encoder)
334 {
335 struct imx_tve *tve = enc_to_tve(encoder);
336
337 tve_disable(tve);
338 }
339
imx_tve_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)340 static int imx_tve_atomic_check(struct drm_encoder *encoder,
341 struct drm_crtc_state *crtc_state,
342 struct drm_connector_state *conn_state)
343 {
344 struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
345 struct imx_tve *tve = enc_to_tve(encoder);
346
347 imx_crtc_state->bus_format = MEDIA_BUS_FMT_GBR888_1X24;
348 imx_crtc_state->di_hsync_pin = tve->di_hsync_pin;
349 imx_crtc_state->di_vsync_pin = tve->di_vsync_pin;
350
351 return 0;
352 }
353
354 static const struct drm_connector_funcs imx_tve_connector_funcs = {
355 .dpms = drm_atomic_helper_connector_dpms,
356 .fill_modes = drm_helper_probe_single_connector_modes,
357 .detect = imx_tve_connector_detect,
358 .destroy = imx_drm_connector_destroy,
359 .reset = drm_atomic_helper_connector_reset,
360 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
361 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
362 };
363
364 static const struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
365 .get_modes = imx_tve_connector_get_modes,
366 .best_encoder = imx_tve_connector_best_encoder,
367 .mode_valid = imx_tve_connector_mode_valid,
368 };
369
370 static const struct drm_encoder_funcs imx_tve_encoder_funcs = {
371 .destroy = imx_drm_encoder_destroy,
372 };
373
374 static const struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
375 .mode_set = imx_tve_encoder_mode_set,
376 .enable = imx_tve_encoder_enable,
377 .disable = imx_tve_encoder_disable,
378 .atomic_check = imx_tve_atomic_check,
379 };
380
imx_tve_irq_handler(int irq,void * data)381 static irqreturn_t imx_tve_irq_handler(int irq, void *data)
382 {
383 struct imx_tve *tve = data;
384 unsigned int val;
385
386 regmap_read(tve->regmap, TVE_STAT_REG, &val);
387
388 /* clear interrupt status register */
389 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
390
391 return IRQ_HANDLED;
392 }
393
clk_tve_di_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)394 static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
395 unsigned long parent_rate)
396 {
397 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
398 unsigned int val;
399 int ret;
400
401 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
402 if (ret < 0)
403 return 0;
404
405 switch (val & TVE_DAC_SAMP_RATE_MASK) {
406 case TVE_DAC_DIV4_RATE:
407 return parent_rate / 4;
408 case TVE_DAC_DIV2_RATE:
409 return parent_rate / 2;
410 case TVE_DAC_FULL_RATE:
411 default:
412 return parent_rate;
413 }
414
415 return 0;
416 }
417
clk_tve_di_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)418 static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
419 unsigned long *prate)
420 {
421 unsigned long div;
422
423 div = *prate / rate;
424 if (div >= 4)
425 return *prate / 4;
426 else if (div >= 2)
427 return *prate / 2;
428 return *prate;
429 }
430
clk_tve_di_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)431 static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
432 unsigned long parent_rate)
433 {
434 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
435 unsigned long div;
436 u32 val;
437 int ret;
438
439 div = parent_rate / rate;
440 if (div >= 4)
441 val = TVE_DAC_DIV4_RATE;
442 else if (div >= 2)
443 val = TVE_DAC_DIV2_RATE;
444 else
445 val = TVE_DAC_FULL_RATE;
446
447 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
448 TVE_DAC_SAMP_RATE_MASK, val);
449
450 if (ret < 0) {
451 dev_err(tve->dev, "failed to set divider: %d\n", ret);
452 return ret;
453 }
454
455 return 0;
456 }
457
458 static struct clk_ops clk_tve_di_ops = {
459 .round_rate = clk_tve_di_round_rate,
460 .set_rate = clk_tve_di_set_rate,
461 .recalc_rate = clk_tve_di_recalc_rate,
462 };
463
tve_clk_init(struct imx_tve * tve,void __iomem * base)464 static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
465 {
466 const char *tve_di_parent[1];
467 struct clk_init_data init = {
468 .name = "tve_di",
469 .ops = &clk_tve_di_ops,
470 .num_parents = 1,
471 .flags = 0,
472 };
473
474 tve_di_parent[0] = __clk_get_name(tve->clk);
475 init.parent_names = (const char **)&tve_di_parent;
476
477 tve->clk_hw_di.init = &init;
478 tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di);
479 if (IS_ERR(tve->di_clk)) {
480 dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
481 PTR_ERR(tve->di_clk));
482 return PTR_ERR(tve->di_clk);
483 }
484
485 return 0;
486 }
487
imx_tve_register(struct drm_device * drm,struct imx_tve * tve)488 static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve)
489 {
490 int encoder_type;
491 int ret;
492
493 encoder_type = tve->mode == TVE_MODE_VGA ?
494 DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
495
496 ret = imx_drm_encoder_parse_of(drm, &tve->encoder, tve->dev->of_node);
497 if (ret)
498 return ret;
499
500 drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs);
501 drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs,
502 encoder_type, NULL);
503
504 drm_connector_helper_add(&tve->connector,
505 &imx_tve_connector_helper_funcs);
506 drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs,
507 DRM_MODE_CONNECTOR_VGA);
508
509 drm_mode_connector_attach_encoder(&tve->connector, &tve->encoder);
510
511 return 0;
512 }
513
imx_tve_readable_reg(struct device * dev,unsigned int reg)514 static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
515 {
516 return (reg % 4 == 0) && (reg <= 0xdc);
517 }
518
519 static struct regmap_config tve_regmap_config = {
520 .reg_bits = 32,
521 .val_bits = 32,
522 .reg_stride = 4,
523
524 .readable_reg = imx_tve_readable_reg,
525
526 .lock = tve_lock,
527 .unlock = tve_unlock,
528
529 .max_register = 0xdc,
530 };
531
532 static const char * const imx_tve_modes[] = {
533 [TVE_MODE_TVOUT] = "tvout",
534 [TVE_MODE_VGA] = "vga",
535 };
536
of_get_tve_mode(struct device_node * np)537 static const int of_get_tve_mode(struct device_node *np)
538 {
539 const char *bm;
540 int ret, i;
541
542 ret = of_property_read_string(np, "fsl,tve-mode", &bm);
543 if (ret < 0)
544 return ret;
545
546 for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
547 if (!strcasecmp(bm, imx_tve_modes[i]))
548 return i;
549
550 return -EINVAL;
551 }
552
imx_tve_bind(struct device * dev,struct device * master,void * data)553 static int imx_tve_bind(struct device *dev, struct device *master, void *data)
554 {
555 struct platform_device *pdev = to_platform_device(dev);
556 struct drm_device *drm = data;
557 struct device_node *np = dev->of_node;
558 struct device_node *ddc_node;
559 struct imx_tve *tve;
560 struct resource *res;
561 void __iomem *base;
562 unsigned int val;
563 int irq;
564 int ret;
565
566 tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
567 if (!tve)
568 return -ENOMEM;
569
570 tve->dev = dev;
571 spin_lock_init(&tve->lock);
572
573 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
574 if (ddc_node) {
575 tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
576 of_node_put(ddc_node);
577 }
578
579 tve->mode = of_get_tve_mode(np);
580 if (tve->mode != TVE_MODE_VGA) {
581 dev_err(dev, "only VGA mode supported, currently\n");
582 return -EINVAL;
583 }
584
585 if (tve->mode == TVE_MODE_VGA) {
586 ret = of_property_read_u32(np, "fsl,hsync-pin",
587 &tve->di_hsync_pin);
588
589 if (ret < 0) {
590 dev_err(dev, "failed to get hsync pin\n");
591 return ret;
592 }
593
594 ret = of_property_read_u32(np, "fsl,vsync-pin",
595 &tve->di_vsync_pin);
596
597 if (ret < 0) {
598 dev_err(dev, "failed to get vsync pin\n");
599 return ret;
600 }
601 }
602
603 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
604 base = devm_ioremap_resource(dev, res);
605 if (IS_ERR(base))
606 return PTR_ERR(base);
607
608 tve_regmap_config.lock_arg = tve;
609 tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
610 &tve_regmap_config);
611 if (IS_ERR(tve->regmap)) {
612 dev_err(dev, "failed to init regmap: %ld\n",
613 PTR_ERR(tve->regmap));
614 return PTR_ERR(tve->regmap);
615 }
616
617 irq = platform_get_irq(pdev, 0);
618 if (irq < 0) {
619 dev_err(dev, "failed to get irq\n");
620 return irq;
621 }
622
623 ret = devm_request_threaded_irq(dev, irq, NULL,
624 imx_tve_irq_handler, IRQF_ONESHOT,
625 "imx-tve", tve);
626 if (ret < 0) {
627 dev_err(dev, "failed to request irq: %d\n", ret);
628 return ret;
629 }
630
631 tve->dac_reg = devm_regulator_get(dev, "dac");
632 if (!IS_ERR(tve->dac_reg)) {
633 if (regulator_get_voltage(tve->dac_reg) != IMX_TVE_DAC_VOLTAGE)
634 dev_warn(dev, "dac voltage is not %d uV\n", IMX_TVE_DAC_VOLTAGE);
635 ret = regulator_enable(tve->dac_reg);
636 if (ret)
637 return ret;
638 }
639
640 tve->clk = devm_clk_get(dev, "tve");
641 if (IS_ERR(tve->clk)) {
642 dev_err(dev, "failed to get high speed tve clock: %ld\n",
643 PTR_ERR(tve->clk));
644 return PTR_ERR(tve->clk);
645 }
646
647 /* this is the IPU DI clock input selector, can be parented to tve_di */
648 tve->di_sel_clk = devm_clk_get(dev, "di_sel");
649 if (IS_ERR(tve->di_sel_clk)) {
650 dev_err(dev, "failed to get ipu di mux clock: %ld\n",
651 PTR_ERR(tve->di_sel_clk));
652 return PTR_ERR(tve->di_sel_clk);
653 }
654
655 ret = tve_clk_init(tve, base);
656 if (ret < 0)
657 return ret;
658
659 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
660 if (ret < 0) {
661 dev_err(dev, "failed to read configuration register: %d\n",
662 ret);
663 return ret;
664 }
665 if (val != 0x00100000) {
666 dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
667 return -ENODEV;
668 }
669
670 /* disable cable detection for VGA mode */
671 ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
672 if (ret)
673 return ret;
674
675 ret = imx_tve_register(drm, tve);
676 if (ret)
677 return ret;
678
679 dev_set_drvdata(dev, tve);
680
681 return 0;
682 }
683
imx_tve_unbind(struct device * dev,struct device * master,void * data)684 static void imx_tve_unbind(struct device *dev, struct device *master,
685 void *data)
686 {
687 struct imx_tve *tve = dev_get_drvdata(dev);
688
689 if (!IS_ERR(tve->dac_reg))
690 regulator_disable(tve->dac_reg);
691 }
692
693 static const struct component_ops imx_tve_ops = {
694 .bind = imx_tve_bind,
695 .unbind = imx_tve_unbind,
696 };
697
imx_tve_probe(struct platform_device * pdev)698 static int imx_tve_probe(struct platform_device *pdev)
699 {
700 return component_add(&pdev->dev, &imx_tve_ops);
701 }
702
imx_tve_remove(struct platform_device * pdev)703 static int imx_tve_remove(struct platform_device *pdev)
704 {
705 component_del(&pdev->dev, &imx_tve_ops);
706 return 0;
707 }
708
709 static const struct of_device_id imx_tve_dt_ids[] = {
710 { .compatible = "fsl,imx53-tve", },
711 { /* sentinel */ }
712 };
713 MODULE_DEVICE_TABLE(of, imx_tve_dt_ids);
714
715 static struct platform_driver imx_tve_driver = {
716 .probe = imx_tve_probe,
717 .remove = imx_tve_remove,
718 .driver = {
719 .of_match_table = imx_tve_dt_ids,
720 .name = "imx-tve",
721 },
722 };
723
724 module_platform_driver(imx_tve_driver);
725
726 MODULE_DESCRIPTION("i.MX Television Encoder driver");
727 MODULE_AUTHOR("Philipp Zabel, Pengutronix");
728 MODULE_LICENSE("GPL");
729 MODULE_ALIAS("platform:imx-tve");
730