1 /*
2 * Copyright (C) 2013-2014 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "adreno_gpu.h"
21
22 #define ANY_ID 0xff
23
24 bool hang_debug = false;
25 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
26 module_param_named(hang_debug, hang_debug, bool, 0600);
27
28 static const struct adreno_info gpulist[] = {
29 {
30 .rev = ADRENO_REV(3, 0, 5, ANY_ID),
31 .revn = 305,
32 .name = "A305",
33 .pm4fw = "a300_pm4.fw",
34 .pfpfw = "a300_pfp.fw",
35 .gmem = SZ_256K,
36 .init = a3xx_gpu_init,
37 }, {
38 .rev = ADRENO_REV(3, 0, 6, 0),
39 .revn = 307, /* because a305c is revn==306 */
40 .name = "A306",
41 .pm4fw = "a300_pm4.fw",
42 .pfpfw = "a300_pfp.fw",
43 .gmem = SZ_128K,
44 .init = a3xx_gpu_init,
45 }, {
46 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
47 .revn = 320,
48 .name = "A320",
49 .pm4fw = "a300_pm4.fw",
50 .pfpfw = "a300_pfp.fw",
51 .gmem = SZ_512K,
52 .init = a3xx_gpu_init,
53 }, {
54 .rev = ADRENO_REV(3, 3, 0, ANY_ID),
55 .revn = 330,
56 .name = "A330",
57 .pm4fw = "a330_pm4.fw",
58 .pfpfw = "a330_pfp.fw",
59 .gmem = SZ_1M,
60 .init = a3xx_gpu_init,
61 }, {
62 .rev = ADRENO_REV(4, 2, 0, ANY_ID),
63 .revn = 420,
64 .name = "A420",
65 .pm4fw = "a420_pm4.fw",
66 .pfpfw = "a420_pfp.fw",
67 .gmem = (SZ_1M + SZ_512K),
68 .init = a4xx_gpu_init,
69 }, {
70 .rev = ADRENO_REV(4, 3, 0, ANY_ID),
71 .revn = 430,
72 .name = "A430",
73 .pm4fw = "a420_pm4.fw",
74 .pfpfw = "a420_pfp.fw",
75 .gmem = (SZ_1M + SZ_512K),
76 .init = a4xx_gpu_init,
77 },
78 };
79
80 MODULE_FIRMWARE("a300_pm4.fw");
81 MODULE_FIRMWARE("a300_pfp.fw");
82 MODULE_FIRMWARE("a330_pm4.fw");
83 MODULE_FIRMWARE("a330_pfp.fw");
84 MODULE_FIRMWARE("a420_pm4.fw");
85 MODULE_FIRMWARE("a420_pfp.fw");
86
_rev_match(uint8_t entry,uint8_t id)87 static inline bool _rev_match(uint8_t entry, uint8_t id)
88 {
89 return (entry == ANY_ID) || (entry == id);
90 }
91
adreno_info(struct adreno_rev rev)92 const struct adreno_info *adreno_info(struct adreno_rev rev)
93 {
94 int i;
95
96 /* identify gpu: */
97 for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
98 const struct adreno_info *info = &gpulist[i];
99 if (_rev_match(info->rev.core, rev.core) &&
100 _rev_match(info->rev.major, rev.major) &&
101 _rev_match(info->rev.minor, rev.minor) &&
102 _rev_match(info->rev.patchid, rev.patchid))
103 return info;
104 }
105
106 return NULL;
107 }
108
adreno_load_gpu(struct drm_device * dev)109 struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
110 {
111 struct msm_drm_private *priv = dev->dev_private;
112 struct platform_device *pdev = priv->gpu_pdev;
113 struct adreno_platform_config *config;
114 struct adreno_rev rev;
115 const struct adreno_info *info;
116 struct msm_gpu *gpu = NULL;
117
118 if (!pdev) {
119 dev_err(dev->dev, "no adreno device\n");
120 return NULL;
121 }
122
123 config = pdev->dev.platform_data;
124 rev = config->rev;
125 info = adreno_info(config->rev);
126
127 if (!info) {
128 dev_warn(dev->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
129 rev.core, rev.major, rev.minor, rev.patchid);
130 return NULL;
131 }
132
133 DBG("Found GPU: %u.%u.%u.%u", rev.core, rev.major,
134 rev.minor, rev.patchid);
135
136 gpu = info->init(dev);
137 if (IS_ERR(gpu)) {
138 dev_warn(dev->dev, "failed to load adreno gpu\n");
139 gpu = NULL;
140 /* not fatal */
141 }
142
143 if (gpu) {
144 int ret;
145 mutex_lock(&dev->struct_mutex);
146 gpu->funcs->pm_resume(gpu);
147 mutex_unlock(&dev->struct_mutex);
148 ret = gpu->funcs->hw_init(gpu);
149 if (ret) {
150 dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
151 gpu->funcs->destroy(gpu);
152 gpu = NULL;
153 } else {
154 /* give inactive pm a chance to kick in: */
155 msm_gpu_retire(gpu);
156 }
157 }
158
159 return gpu;
160 }
161
set_gpu_pdev(struct drm_device * dev,struct platform_device * pdev)162 static void set_gpu_pdev(struct drm_device *dev,
163 struct platform_device *pdev)
164 {
165 struct msm_drm_private *priv = dev->dev_private;
166 priv->gpu_pdev = pdev;
167 }
168
adreno_bind(struct device * dev,struct device * master,void * data)169 static int adreno_bind(struct device *dev, struct device *master, void *data)
170 {
171 static struct adreno_platform_config config = {};
172 struct device_node *child, *node = dev->of_node;
173 u32 val;
174 int ret;
175
176 ret = of_property_read_u32(node, "qcom,chipid", &val);
177 if (ret) {
178 dev_err(dev, "could not find chipid: %d\n", ret);
179 return ret;
180 }
181
182 config.rev = ADRENO_REV((val >> 24) & 0xff,
183 (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff);
184
185 /* find clock rates: */
186 config.fast_rate = 0;
187 config.slow_rate = ~0;
188 for_each_child_of_node(node, child) {
189 if (of_device_is_compatible(child, "qcom,gpu-pwrlevels")) {
190 struct device_node *pwrlvl;
191 for_each_child_of_node(child, pwrlvl) {
192 ret = of_property_read_u32(pwrlvl, "qcom,gpu-freq", &val);
193 if (ret) {
194 dev_err(dev, "could not find gpu-freq: %d\n", ret);
195 return ret;
196 }
197 config.fast_rate = max(config.fast_rate, val);
198 config.slow_rate = min(config.slow_rate, val);
199 }
200 }
201 }
202
203 if (!config.fast_rate) {
204 dev_err(dev, "could not find clk rates\n");
205 return -ENXIO;
206 }
207
208 dev->platform_data = &config;
209 set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev));
210 return 0;
211 }
212
adreno_unbind(struct device * dev,struct device * master,void * data)213 static void adreno_unbind(struct device *dev, struct device *master,
214 void *data)
215 {
216 set_gpu_pdev(dev_get_drvdata(master), NULL);
217 }
218
219 static const struct component_ops a3xx_ops = {
220 .bind = adreno_bind,
221 .unbind = adreno_unbind,
222 };
223
adreno_probe(struct platform_device * pdev)224 static int adreno_probe(struct platform_device *pdev)
225 {
226 return component_add(&pdev->dev, &a3xx_ops);
227 }
228
adreno_remove(struct platform_device * pdev)229 static int adreno_remove(struct platform_device *pdev)
230 {
231 component_del(&pdev->dev, &a3xx_ops);
232 return 0;
233 }
234
235 static const struct of_device_id dt_match[] = {
236 { .compatible = "qcom,adreno-3xx" },
237 /* for backwards compat w/ downstream kgsl DT files: */
238 { .compatible = "qcom,kgsl-3d0" },
239 {}
240 };
241
242 static struct platform_driver adreno_driver = {
243 .probe = adreno_probe,
244 .remove = adreno_remove,
245 .driver = {
246 .name = "adreno",
247 .of_match_table = dt_match,
248 },
249 };
250
adreno_register(void)251 void __init adreno_register(void)
252 {
253 platform_driver_register(&adreno_driver);
254 }
255
adreno_unregister(void)256 void __exit adreno_unregister(void)
257 {
258 platform_driver_unregister(&adreno_driver);
259 }
260