1 /*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24 #include "gf100.h"
25 #include "ctxgf100.h"
26
27 #include <subdev/fb.h>
28
29 #include <nvif/class.h>
30
31 /*******************************************************************************
32 * PGRAPH register lists
33 ******************************************************************************/
34
35 const struct gf100_gr_init
36 gk104_gr_init_main_0[] = {
37 { 0x400080, 1, 0x04, 0x003083c2 },
38 { 0x400088, 1, 0x04, 0x0001ffe7 },
39 { 0x40008c, 1, 0x04, 0x00000000 },
40 { 0x400090, 1, 0x04, 0x00000030 },
41 { 0x40013c, 1, 0x04, 0x003901f7 },
42 { 0x400140, 1, 0x04, 0x00000100 },
43 { 0x400144, 1, 0x04, 0x00000000 },
44 { 0x400148, 1, 0x04, 0x00000110 },
45 { 0x400138, 1, 0x04, 0x00000000 },
46 { 0x400130, 2, 0x04, 0x00000000 },
47 { 0x400124, 1, 0x04, 0x00000002 },
48 {}
49 };
50
51 static const struct gf100_gr_init
52 gk104_gr_init_ds_0[] = {
53 { 0x405844, 1, 0x04, 0x00ffffff },
54 { 0x405850, 1, 0x04, 0x00000000 },
55 { 0x405900, 1, 0x04, 0x0000ff34 },
56 { 0x405908, 1, 0x04, 0x00000000 },
57 { 0x405928, 2, 0x04, 0x00000000 },
58 {}
59 };
60
61 static const struct gf100_gr_init
62 gk104_gr_init_sked_0[] = {
63 { 0x407010, 1, 0x04, 0x00000000 },
64 {}
65 };
66
67 static const struct gf100_gr_init
68 gk104_gr_init_cwd_0[] = {
69 { 0x405b50, 1, 0x04, 0x00000000 },
70 {}
71 };
72
73 static const struct gf100_gr_init
74 gk104_gr_init_gpc_unk_1[] = {
75 { 0x418d00, 1, 0x04, 0x00000000 },
76 { 0x418d28, 2, 0x04, 0x00000000 },
77 { 0x418f00, 1, 0x04, 0x00000000 },
78 { 0x418f08, 1, 0x04, 0x00000000 },
79 { 0x418f20, 2, 0x04, 0x00000000 },
80 { 0x418e00, 1, 0x04, 0x00000060 },
81 { 0x418e08, 1, 0x04, 0x00000000 },
82 { 0x418e1c, 2, 0x04, 0x00000000 },
83 {}
84 };
85
86 const struct gf100_gr_init
87 gk104_gr_init_tpccs_0[] = {
88 { 0x419d0c, 1, 0x04, 0x00000000 },
89 { 0x419d10, 1, 0x04, 0x00000014 },
90 {}
91 };
92
93 const struct gf100_gr_init
94 gk104_gr_init_pe_0[] = {
95 { 0x41980c, 1, 0x04, 0x00000010 },
96 { 0x419844, 1, 0x04, 0x00000000 },
97 { 0x419850, 1, 0x04, 0x00000004 },
98 { 0x419854, 2, 0x04, 0x00000000 },
99 {}
100 };
101
102 static const struct gf100_gr_init
103 gk104_gr_init_l1c_0[] = {
104 { 0x419c98, 1, 0x04, 0x00000000 },
105 { 0x419ca8, 1, 0x04, 0x00000000 },
106 { 0x419cb0, 1, 0x04, 0x01000000 },
107 { 0x419cb4, 1, 0x04, 0x00000000 },
108 { 0x419cb8, 1, 0x04, 0x00b08bea },
109 { 0x419c84, 1, 0x04, 0x00010384 },
110 { 0x419cbc, 1, 0x04, 0x28137646 },
111 { 0x419cc0, 2, 0x04, 0x00000000 },
112 { 0x419c80, 1, 0x04, 0x00020232 },
113 {}
114 };
115
116 static const struct gf100_gr_init
117 gk104_gr_init_sm_0[] = {
118 { 0x419e00, 1, 0x04, 0x00000000 },
119 { 0x419ea0, 1, 0x04, 0x00000000 },
120 { 0x419ee4, 1, 0x04, 0x00000000 },
121 { 0x419ea4, 1, 0x04, 0x00000100 },
122 { 0x419ea8, 1, 0x04, 0x00000000 },
123 { 0x419eb4, 4, 0x04, 0x00000000 },
124 { 0x419edc, 1, 0x04, 0x00000000 },
125 { 0x419f00, 1, 0x04, 0x00000000 },
126 { 0x419f74, 1, 0x04, 0x00000555 },
127 {}
128 };
129
130 const struct gf100_gr_init
131 gk104_gr_init_be_0[] = {
132 { 0x40880c, 1, 0x04, 0x00000000 },
133 { 0x408850, 1, 0x04, 0x00000004 },
134 { 0x408910, 9, 0x04, 0x00000000 },
135 { 0x408950, 1, 0x04, 0x00000000 },
136 { 0x408954, 1, 0x04, 0x0000ffff },
137 { 0x408958, 1, 0x04, 0x00000034 },
138 { 0x408984, 1, 0x04, 0x00000000 },
139 { 0x408988, 1, 0x04, 0x08040201 },
140 { 0x40898c, 1, 0x04, 0x80402010 },
141 {}
142 };
143
144 const struct gf100_gr_pack
145 gk104_gr_pack_mmio[] = {
146 { gk104_gr_init_main_0 },
147 { gf100_gr_init_fe_0 },
148 { gf100_gr_init_pri_0 },
149 { gf100_gr_init_rstr2d_0 },
150 { gf119_gr_init_pd_0 },
151 { gk104_gr_init_ds_0 },
152 { gf100_gr_init_scc_0 },
153 { gk104_gr_init_sked_0 },
154 { gk104_gr_init_cwd_0 },
155 { gf119_gr_init_prop_0 },
156 { gf108_gr_init_gpc_unk_0 },
157 { gf100_gr_init_setup_0 },
158 { gf100_gr_init_crstr_0 },
159 { gf108_gr_init_setup_1 },
160 { gf100_gr_init_zcull_0 },
161 { gf119_gr_init_gpm_0 },
162 { gk104_gr_init_gpc_unk_1 },
163 { gf100_gr_init_gcc_0 },
164 { gk104_gr_init_tpccs_0 },
165 { gf119_gr_init_tex_0 },
166 { gk104_gr_init_pe_0 },
167 { gk104_gr_init_l1c_0 },
168 { gf100_gr_init_mpc_0 },
169 { gk104_gr_init_sm_0 },
170 { gf117_gr_init_pes_0 },
171 { gf117_gr_init_wwdx_0 },
172 { gf117_gr_init_cbm_0 },
173 { gk104_gr_init_be_0 },
174 { gf100_gr_init_fe_1 },
175 {}
176 };
177
178 /*******************************************************************************
179 * PGRAPH engine/subdev functions
180 ******************************************************************************/
181
182 void
gk104_gr_init_rop_active_fbps(struct gf100_gr * gr)183 gk104_gr_init_rop_active_fbps(struct gf100_gr *gr)
184 {
185 struct nvkm_device *device = gr->base.engine.subdev.device;
186 const u32 fbp_count = nvkm_rd32(device, 0x120074);
187 nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */
188 nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */
189 }
190
191 void
gk104_gr_init_ppc_exceptions(struct gf100_gr * gr)192 gk104_gr_init_ppc_exceptions(struct gf100_gr *gr)
193 {
194 struct nvkm_device *device = gr->base.engine.subdev.device;
195 int gpc, ppc;
196
197 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
198 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) {
199 if (!(gr->ppc_mask[gpc] & (1 << ppc)))
200 continue;
201 nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000);
202 }
203 }
204 }
205
206 int
gk104_gr_init(struct gf100_gr * gr)207 gk104_gr_init(struct gf100_gr *gr)
208 {
209 struct nvkm_device *device = gr->base.engine.subdev.device;
210 struct nvkm_fb *fb = device->fb;
211 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
212 u32 data[TPC_MAX / 8] = {};
213 u8 tpcnr[GPC_MAX];
214 int gpc, tpc, rop;
215 int i;
216
217 nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000);
218 nvkm_wr32(device, GPC_BCAST(0x08a4), 0x00000000);
219 nvkm_wr32(device, GPC_BCAST(0x0888), 0x00000000);
220 nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000);
221 nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000);
222 nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000);
223 nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(fb->mmu_wr) >> 8);
224 nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(fb->mmu_rd) >> 8);
225
226 gf100_gr_mmio(gr, gr->func->mmio);
227
228 nvkm_wr32(device, GPC_UNIT(0, 0x3018), 0x00000001);
229
230 memset(data, 0x00, sizeof(data));
231 memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
232 for (i = 0, gpc = -1; i < gr->tpc_total; i++) {
233 do {
234 gpc = (gpc + 1) % gr->gpc_nr;
235 } while (!tpcnr[gpc]);
236 tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
237
238 data[i / 8] |= tpc << ((i % 8) * 4);
239 }
240
241 nvkm_wr32(device, GPC_BCAST(0x0980), data[0]);
242 nvkm_wr32(device, GPC_BCAST(0x0984), data[1]);
243 nvkm_wr32(device, GPC_BCAST(0x0988), data[2]);
244 nvkm_wr32(device, GPC_BCAST(0x098c), data[3]);
245
246 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
247 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
248 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
249 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
250 gr->tpc_total);
251 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
252 }
253
254 nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
255 nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
256
257 gr->func->init_rop_active_fbps(gr);
258
259 nvkm_wr32(device, 0x400500, 0x00010001);
260
261 nvkm_wr32(device, 0x400100, 0xffffffff);
262 nvkm_wr32(device, 0x40013c, 0xffffffff);
263
264 nvkm_wr32(device, 0x409ffc, 0x00000000);
265 nvkm_wr32(device, 0x409c14, 0x00003e3e);
266 nvkm_wr32(device, 0x409c24, 0x000f0001);
267 nvkm_wr32(device, 0x404000, 0xc0000000);
268 nvkm_wr32(device, 0x404600, 0xc0000000);
269 nvkm_wr32(device, 0x408030, 0xc0000000);
270 nvkm_wr32(device, 0x404490, 0xc0000000);
271 nvkm_wr32(device, 0x406018, 0xc0000000);
272 nvkm_wr32(device, 0x407020, 0x40000000);
273 nvkm_wr32(device, 0x405840, 0xc0000000);
274 nvkm_wr32(device, 0x405844, 0x00ffffff);
275 nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
276 nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000);
277
278 gr->func->init_ppc_exceptions(gr);
279
280 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
281 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
282 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
283 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
284 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
285 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
286 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
287 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
288 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
289 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
290 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
291 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
292 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
293 }
294 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
295 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
296 }
297
298 for (rop = 0; rop < gr->rop_nr; rop++) {
299 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000);
300 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000);
301 nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff);
302 nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff);
303 }
304
305 nvkm_wr32(device, 0x400108, 0xffffffff);
306 nvkm_wr32(device, 0x400138, 0xffffffff);
307 nvkm_wr32(device, 0x400118, 0xffffffff);
308 nvkm_wr32(device, 0x400130, 0xffffffff);
309 nvkm_wr32(device, 0x40011c, 0xffffffff);
310 nvkm_wr32(device, 0x400134, 0xffffffff);
311
312 nvkm_wr32(device, 0x400054, 0x34ce3464);
313
314 gf100_gr_zbc_init(gr);
315
316 return gf100_gr_init_ctxctl(gr);
317 }
318
319 #include "fuc/hubgk104.fuc3.h"
320
321 static struct gf100_gr_ucode
322 gk104_gr_fecs_ucode = {
323 .code.data = gk104_grhub_code,
324 .code.size = sizeof(gk104_grhub_code),
325 .data.data = gk104_grhub_data,
326 .data.size = sizeof(gk104_grhub_data),
327 };
328
329 #include "fuc/gpcgk104.fuc3.h"
330
331 static struct gf100_gr_ucode
332 gk104_gr_gpccs_ucode = {
333 .code.data = gk104_grgpc_code,
334 .code.size = sizeof(gk104_grgpc_code),
335 .data.data = gk104_grgpc_data,
336 .data.size = sizeof(gk104_grgpc_data),
337 };
338
339 static const struct gf100_gr_func
340 gk104_gr = {
341 .init = gk104_gr_init,
342 .init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
343 .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
344 .mmio = gk104_gr_pack_mmio,
345 .fecs.ucode = &gk104_gr_fecs_ucode,
346 .gpccs.ucode = &gk104_gr_gpccs_ucode,
347 .rops = gf100_gr_rops,
348 .ppc_nr = 1,
349 .grctx = &gk104_grctx,
350 .sclass = {
351 { -1, -1, FERMI_TWOD_A },
352 { -1, -1, KEPLER_INLINE_TO_MEMORY_A },
353 { -1, -1, KEPLER_A, &gf100_fermi },
354 { -1, -1, KEPLER_COMPUTE_A },
355 {}
356 }
357 };
358
359 int
gk104_gr_new(struct nvkm_device * device,int index,struct nvkm_gr ** pgr)360 gk104_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
361 {
362 return gf100_gr_new_(&gk104_gr, device, index, pgr);
363 }
364