1 /*
2 * Copyright (C) 2007-2012 ST-Ericsson AB
3 * License terms: GNU General Public License (GPL) version 2
4 * ST DDC I2C master mode driver, used in e.g. U300 series platforms.
5 * Author: Linus Walleij <linus.walleij@stericsson.com>
6 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
7 */
8 #include <linux/init.h>
9 #include <linux/module.h>
10 #include <linux/platform_device.h>
11 #include <linux/delay.h>
12 #include <linux/i2c.h>
13 #include <linux/spinlock.h>
14 #include <linux/completion.h>
15 #include <linux/err.h>
16 #include <linux/interrupt.h>
17 #include <linux/clk.h>
18 #include <linux/io.h>
19 #include <linux/slab.h>
20
21 /* the name of this kernel module */
22 #define NAME "stu300"
23
24 /* CR (Control Register) 8bit (R/W) */
25 #define I2C_CR (0x00000000)
26 #define I2C_CR_RESET_VALUE (0x00)
27 #define I2C_CR_RESET_UMASK (0x00)
28 #define I2C_CR_DDC1_ENABLE (0x80)
29 #define I2C_CR_TRANS_ENABLE (0x40)
30 #define I2C_CR_PERIPHERAL_ENABLE (0x20)
31 #define I2C_CR_DDC2B_ENABLE (0x10)
32 #define I2C_CR_START_ENABLE (0x08)
33 #define I2C_CR_ACK_ENABLE (0x04)
34 #define I2C_CR_STOP_ENABLE (0x02)
35 #define I2C_CR_INTERRUPT_ENABLE (0x01)
36 /* SR1 (Status Register 1) 8bit (R/-) */
37 #define I2C_SR1 (0x00000004)
38 #define I2C_SR1_RESET_VALUE (0x00)
39 #define I2C_SR1_RESET_UMASK (0x00)
40 #define I2C_SR1_EVF_IND (0x80)
41 #define I2C_SR1_ADD10_IND (0x40)
42 #define I2C_SR1_TRA_IND (0x20)
43 #define I2C_SR1_BUSY_IND (0x10)
44 #define I2C_SR1_BTF_IND (0x08)
45 #define I2C_SR1_ADSL_IND (0x04)
46 #define I2C_SR1_MSL_IND (0x02)
47 #define I2C_SR1_SB_IND (0x01)
48 /* SR2 (Status Register 2) 8bit (R/-) */
49 #define I2C_SR2 (0x00000008)
50 #define I2C_SR2_RESET_VALUE (0x00)
51 #define I2C_SR2_RESET_UMASK (0x40)
52 #define I2C_SR2_MASK (0xBF)
53 #define I2C_SR2_SCLFAL_IND (0x80)
54 #define I2C_SR2_ENDAD_IND (0x20)
55 #define I2C_SR2_AF_IND (0x10)
56 #define I2C_SR2_STOPF_IND (0x08)
57 #define I2C_SR2_ARLO_IND (0x04)
58 #define I2C_SR2_BERR_IND (0x02)
59 #define I2C_SR2_DDC2BF_IND (0x01)
60 /* CCR (Clock Control Register) 8bit (R/W) */
61 #define I2C_CCR (0x0000000C)
62 #define I2C_CCR_RESET_VALUE (0x00)
63 #define I2C_CCR_RESET_UMASK (0x00)
64 #define I2C_CCR_MASK (0xFF)
65 #define I2C_CCR_FMSM (0x80)
66 #define I2C_CCR_CC_MASK (0x7F)
67 /* OAR1 (Own Address Register 1) 8bit (R/W) */
68 #define I2C_OAR1 (0x00000010)
69 #define I2C_OAR1_RESET_VALUE (0x00)
70 #define I2C_OAR1_RESET_UMASK (0x00)
71 #define I2C_OAR1_ADD_MASK (0xFF)
72 /* OAR2 (Own Address Register 2) 8bit (R/W) */
73 #define I2C_OAR2 (0x00000014)
74 #define I2C_OAR2_RESET_VALUE (0x40)
75 #define I2C_OAR2_RESET_UMASK (0x19)
76 #define I2C_OAR2_MASK (0xE6)
77 #define I2C_OAR2_FR_25_10MHZ (0x00)
78 #define I2C_OAR2_FR_10_1667MHZ (0x20)
79 #define I2C_OAR2_FR_1667_2667MHZ (0x40)
80 #define I2C_OAR2_FR_2667_40MHZ (0x60)
81 #define I2C_OAR2_FR_40_5333MHZ (0x80)
82 #define I2C_OAR2_FR_5333_66MHZ (0xA0)
83 #define I2C_OAR2_FR_66_80MHZ (0xC0)
84 #define I2C_OAR2_FR_80_100MHZ (0xE0)
85 #define I2C_OAR2_FR_MASK (0xE0)
86 #define I2C_OAR2_ADD_MASK (0x06)
87 /* DR (Data Register) 8bit (R/W) */
88 #define I2C_DR (0x00000018)
89 #define I2C_DR_RESET_VALUE (0x00)
90 #define I2C_DR_RESET_UMASK (0xFF)
91 #define I2C_DR_D_MASK (0xFF)
92 /* ECCR (Extended Clock Control Register) 8bit (R/W) */
93 #define I2C_ECCR (0x0000001C)
94 #define I2C_ECCR_RESET_VALUE (0x00)
95 #define I2C_ECCR_RESET_UMASK (0xE0)
96 #define I2C_ECCR_MASK (0x1F)
97 #define I2C_ECCR_CC_MASK (0x1F)
98
99 /*
100 * These events are more or less responses to commands
101 * sent into the hardware, presumably reflecting the state
102 * of an internal state machine.
103 */
104 enum stu300_event {
105 STU300_EVENT_NONE = 0,
106 STU300_EVENT_1,
107 STU300_EVENT_2,
108 STU300_EVENT_3,
109 STU300_EVENT_4,
110 STU300_EVENT_5,
111 STU300_EVENT_6,
112 STU300_EVENT_7,
113 STU300_EVENT_8,
114 STU300_EVENT_9
115 };
116
117 enum stu300_error {
118 STU300_ERROR_NONE = 0,
119 STU300_ERROR_ACKNOWLEDGE_FAILURE,
120 STU300_ERROR_BUS_ERROR,
121 STU300_ERROR_ARBITRATION_LOST,
122 STU300_ERROR_UNKNOWN
123 };
124
125 /* timeout waiting for the controller to respond */
126 #define STU300_TIMEOUT (msecs_to_jiffies(1000))
127
128 /*
129 * The number of address send athemps tried before giving up.
130 * If the first one failes it seems like 5 to 8 attempts are required.
131 */
132 #define NUM_ADDR_RESEND_ATTEMPTS 12
133
134 /* I2C clock speed, in Hz 0-400kHz*/
135 static unsigned int scl_frequency = 100000;
136 module_param(scl_frequency, uint, 0644);
137
138 /**
139 * struct stu300_dev - the stu300 driver state holder
140 * @pdev: parent platform device
141 * @adapter: corresponding I2C adapter
142 * @clk: hardware block clock
143 * @irq: assigned interrupt line
144 * @cmd_issue_lock: this locks the following cmd_ variables
145 * @cmd_complete: acknowledge completion for an I2C command
146 * @cmd_event: expected event coming in as a response to a command
147 * @cmd_err: error code as response to a command
148 * @speed: current bus speed in Hz
149 * @msg_index: index of current message
150 * @msg_len: length of current message
151 */
152
153 struct stu300_dev {
154 struct platform_device *pdev;
155 struct i2c_adapter adapter;
156 void __iomem *virtbase;
157 struct clk *clk;
158 int irq;
159 spinlock_t cmd_issue_lock;
160 struct completion cmd_complete;
161 enum stu300_event cmd_event;
162 enum stu300_error cmd_err;
163 unsigned int speed;
164 int msg_index;
165 int msg_len;
166 };
167
168 /* Local forward function declarations */
169 static int stu300_init_hw(struct stu300_dev *dev);
170
171 /*
172 * The block needs writes in both MSW and LSW in order
173 * for all data lines to reach their destination.
174 */
stu300_wr8(u32 value,void __iomem * address)175 static inline void stu300_wr8(u32 value, void __iomem *address)
176 {
177 writel((value << 16) | value, address);
178 }
179
180 /*
181 * This merely masks off the duplicates which appear
182 * in bytes 1-3. You _MUST_ use 32-bit bus access on this
183 * device, else it will not work.
184 */
stu300_r8(void __iomem * address)185 static inline u32 stu300_r8(void __iomem *address)
186 {
187 return readl(address) & 0x000000FFU;
188 }
189
stu300_irq_enable(struct stu300_dev * dev)190 static void stu300_irq_enable(struct stu300_dev *dev)
191 {
192 u32 val;
193 val = stu300_r8(dev->virtbase + I2C_CR);
194 val |= I2C_CR_INTERRUPT_ENABLE;
195 /* Twice paranoia (possible HW glitch) */
196 stu300_wr8(val, dev->virtbase + I2C_CR);
197 stu300_wr8(val, dev->virtbase + I2C_CR);
198 }
199
stu300_irq_disable(struct stu300_dev * dev)200 static void stu300_irq_disable(struct stu300_dev *dev)
201 {
202 u32 val;
203 val = stu300_r8(dev->virtbase + I2C_CR);
204 val &= ~I2C_CR_INTERRUPT_ENABLE;
205 /* Twice paranoia (possible HW glitch) */
206 stu300_wr8(val, dev->virtbase + I2C_CR);
207 stu300_wr8(val, dev->virtbase + I2C_CR);
208 }
209
210
211 /*
212 * Tells whether a certain event or events occurred in
213 * response to a command. The events represent states in
214 * the internal state machine of the hardware. The events
215 * are not very well described in the hardware
216 * documentation and can only be treated as abstract state
217 * machine states.
218 *
219 * @ret 0 = event has not occurred or unknown error, any
220 * other value means the correct event occurred or an error.
221 */
222
stu300_event_occurred(struct stu300_dev * dev,enum stu300_event mr_event)223 static int stu300_event_occurred(struct stu300_dev *dev,
224 enum stu300_event mr_event) {
225 u32 status1;
226 u32 status2;
227
228 /* What event happened? */
229 status1 = stu300_r8(dev->virtbase + I2C_SR1);
230
231 if (!(status1 & I2C_SR1_EVF_IND))
232 /* No event at all */
233 return 0;
234
235 status2 = stu300_r8(dev->virtbase + I2C_SR2);
236
237 /* Block any multiple interrupts */
238 stu300_irq_disable(dev);
239
240 /* Check for errors first */
241 if (status2 & I2C_SR2_AF_IND) {
242 dev->cmd_err = STU300_ERROR_ACKNOWLEDGE_FAILURE;
243 return 1;
244 } else if (status2 & I2C_SR2_BERR_IND) {
245 dev->cmd_err = STU300_ERROR_BUS_ERROR;
246 return 1;
247 } else if (status2 & I2C_SR2_ARLO_IND) {
248 dev->cmd_err = STU300_ERROR_ARBITRATION_LOST;
249 return 1;
250 }
251
252 switch (mr_event) {
253 case STU300_EVENT_1:
254 if (status1 & I2C_SR1_ADSL_IND)
255 return 1;
256 break;
257 case STU300_EVENT_2:
258 case STU300_EVENT_3:
259 case STU300_EVENT_7:
260 case STU300_EVENT_8:
261 if (status1 & I2C_SR1_BTF_IND) {
262 return 1;
263 }
264 break;
265 case STU300_EVENT_4:
266 if (status2 & I2C_SR2_STOPF_IND)
267 return 1;
268 break;
269 case STU300_EVENT_5:
270 if (status1 & I2C_SR1_SB_IND)
271 /* Clear start bit */
272 return 1;
273 break;
274 case STU300_EVENT_6:
275 if (status2 & I2C_SR2_ENDAD_IND) {
276 /* First check for any errors */
277 return 1;
278 }
279 break;
280 case STU300_EVENT_9:
281 if (status1 & I2C_SR1_ADD10_IND)
282 return 1;
283 break;
284 default:
285 break;
286 }
287 /* If we get here, we're on thin ice.
288 * Here we are in a status where we have
289 * gotten a response that does not match
290 * what we requested.
291 */
292 dev->cmd_err = STU300_ERROR_UNKNOWN;
293 dev_err(&dev->pdev->dev,
294 "Unhandled interrupt! %d sr1: 0x%x sr2: 0x%x\n",
295 mr_event, status1, status2);
296 return 0;
297 }
298
stu300_irh(int irq,void * data)299 static irqreturn_t stu300_irh(int irq, void *data)
300 {
301 struct stu300_dev *dev = data;
302 int res;
303
304 /* Just make sure that the block is clocked */
305 clk_enable(dev->clk);
306
307 /* See if this was what we were waiting for */
308 spin_lock(&dev->cmd_issue_lock);
309
310 res = stu300_event_occurred(dev, dev->cmd_event);
311 if (res || dev->cmd_err != STU300_ERROR_NONE)
312 complete(&dev->cmd_complete);
313
314 spin_unlock(&dev->cmd_issue_lock);
315
316 clk_disable(dev->clk);
317
318 return IRQ_HANDLED;
319 }
320
321 /*
322 * Sends a command and then waits for the bits masked by *flagmask*
323 * to go high or low by IRQ awaiting.
324 */
stu300_start_and_await_event(struct stu300_dev * dev,u8 cr_value,enum stu300_event mr_event)325 static int stu300_start_and_await_event(struct stu300_dev *dev,
326 u8 cr_value,
327 enum stu300_event mr_event)
328 {
329 int ret;
330
331 if (unlikely(irqs_disabled())) {
332 /* TODO: implement polling for this case if need be. */
333 WARN(1, "irqs are disabled, cannot poll for event\n");
334 return -EIO;
335 }
336
337 /* Lock command issue, fill in an event we wait for */
338 spin_lock_irq(&dev->cmd_issue_lock);
339 init_completion(&dev->cmd_complete);
340 dev->cmd_err = STU300_ERROR_NONE;
341 dev->cmd_event = mr_event;
342 spin_unlock_irq(&dev->cmd_issue_lock);
343
344 /* Turn on interrupt, send command and wait. */
345 cr_value |= I2C_CR_INTERRUPT_ENABLE;
346 stu300_wr8(cr_value, dev->virtbase + I2C_CR);
347 ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
348 STU300_TIMEOUT);
349 if (ret < 0) {
350 dev_err(&dev->pdev->dev,
351 "wait_for_completion_interruptible_timeout() "
352 "returned %d waiting for event %04x\n", ret, mr_event);
353 return ret;
354 }
355
356 if (ret == 0) {
357 dev_err(&dev->pdev->dev, "controller timed out "
358 "waiting for event %d, reinit hardware\n", mr_event);
359 (void) stu300_init_hw(dev);
360 return -ETIMEDOUT;
361 }
362
363 if (dev->cmd_err != STU300_ERROR_NONE) {
364 dev_err(&dev->pdev->dev, "controller (start) "
365 "error %d waiting for event %d, reinit hardware\n",
366 dev->cmd_err, mr_event);
367 (void) stu300_init_hw(dev);
368 return -EIO;
369 }
370
371 return 0;
372 }
373
374 /*
375 * This waits for a flag to be set, if it is not set on entry, an interrupt is
376 * configured to wait for the flag using a completion.
377 */
stu300_await_event(struct stu300_dev * dev,enum stu300_event mr_event)378 static int stu300_await_event(struct stu300_dev *dev,
379 enum stu300_event mr_event)
380 {
381 int ret;
382
383 if (unlikely(irqs_disabled())) {
384 /* TODO: implement polling for this case if need be. */
385 dev_err(&dev->pdev->dev, "irqs are disabled on this "
386 "system!\n");
387 return -EIO;
388 }
389
390 /* Is it already here? */
391 spin_lock_irq(&dev->cmd_issue_lock);
392 dev->cmd_err = STU300_ERROR_NONE;
393 dev->cmd_event = mr_event;
394
395 init_completion(&dev->cmd_complete);
396
397 /* Turn on the I2C interrupt for current operation */
398 stu300_irq_enable(dev);
399
400 /* Unlock the command block and wait for the event to occur */
401 spin_unlock_irq(&dev->cmd_issue_lock);
402
403 ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
404 STU300_TIMEOUT);
405 if (ret < 0) {
406 dev_err(&dev->pdev->dev,
407 "wait_for_completion_interruptible_timeout()"
408 "returned %d waiting for event %04x\n", ret, mr_event);
409 return ret;
410 }
411
412 if (ret == 0) {
413 if (mr_event != STU300_EVENT_6) {
414 dev_err(&dev->pdev->dev, "controller "
415 "timed out waiting for event %d, reinit "
416 "hardware\n", mr_event);
417 (void) stu300_init_hw(dev);
418 }
419 return -ETIMEDOUT;
420 }
421
422 if (dev->cmd_err != STU300_ERROR_NONE) {
423 if (mr_event != STU300_EVENT_6) {
424 dev_err(&dev->pdev->dev, "controller "
425 "error (await_event) %d waiting for event %d, "
426 "reinit hardware\n", dev->cmd_err, mr_event);
427 (void) stu300_init_hw(dev);
428 }
429 return -EIO;
430 }
431
432 return 0;
433 }
434
435 /*
436 * Waits for the busy bit to go low by repeated polling.
437 */
438 #define BUSY_RELEASE_ATTEMPTS 10
stu300_wait_while_busy(struct stu300_dev * dev)439 static int stu300_wait_while_busy(struct stu300_dev *dev)
440 {
441 unsigned long timeout;
442 int i;
443
444 for (i = 0; i < BUSY_RELEASE_ATTEMPTS; i++) {
445 timeout = jiffies + STU300_TIMEOUT;
446
447 while (!time_after(jiffies, timeout)) {
448 /* Is not busy? */
449 if ((stu300_r8(dev->virtbase + I2C_SR1) &
450 I2C_SR1_BUSY_IND) == 0)
451 return 0;
452 msleep(1);
453 }
454
455 dev_err(&dev->pdev->dev, "transaction timed out "
456 "waiting for device to be free (not busy). "
457 "Attempt: %d\n", i+1);
458
459 dev_err(&dev->pdev->dev, "base address = "
460 "0x%08x, reinit hardware\n", (u32) dev->virtbase);
461
462 (void) stu300_init_hw(dev);
463 }
464
465 dev_err(&dev->pdev->dev, "giving up after %d attempts "
466 "to reset the bus.\n", BUSY_RELEASE_ATTEMPTS);
467
468 return -ETIMEDOUT;
469 }
470
471 struct stu300_clkset {
472 unsigned long rate;
473 u32 setting;
474 };
475
476 static const struct stu300_clkset stu300_clktable[] = {
477 { 0, 0xFFU },
478 { 2500000, I2C_OAR2_FR_25_10MHZ },
479 { 10000000, I2C_OAR2_FR_10_1667MHZ },
480 { 16670000, I2C_OAR2_FR_1667_2667MHZ },
481 { 26670000, I2C_OAR2_FR_2667_40MHZ },
482 { 40000000, I2C_OAR2_FR_40_5333MHZ },
483 { 53330000, I2C_OAR2_FR_5333_66MHZ },
484 { 66000000, I2C_OAR2_FR_66_80MHZ },
485 { 80000000, I2C_OAR2_FR_80_100MHZ },
486 { 100000000, 0xFFU },
487 };
488
489
stu300_set_clk(struct stu300_dev * dev,unsigned long clkrate)490 static int stu300_set_clk(struct stu300_dev *dev, unsigned long clkrate)
491 {
492
493 u32 val;
494 int i = 0;
495
496 /* Locate the appropriate clock setting */
497 while (i < ARRAY_SIZE(stu300_clktable) - 1 &&
498 stu300_clktable[i].rate < clkrate)
499 i++;
500
501 if (stu300_clktable[i].setting == 0xFFU) {
502 dev_err(&dev->pdev->dev, "too %s clock rate requested "
503 "(%lu Hz).\n", i ? "high" : "low", clkrate);
504 return -EINVAL;
505 }
506
507 stu300_wr8(stu300_clktable[i].setting,
508 dev->virtbase + I2C_OAR2);
509
510 dev_dbg(&dev->pdev->dev, "Clock rate %lu Hz, I2C bus speed %d Hz "
511 "virtbase %p\n", clkrate, dev->speed, dev->virtbase);
512
513 if (dev->speed > 100000)
514 /* Fast Mode I2C */
515 val = ((clkrate/dev->speed) - 9)/3 + 1;
516 else
517 /* Standard Mode I2C */
518 val = ((clkrate/dev->speed) - 7)/2 + 1;
519
520 /* According to spec the divider must be > 2 */
521 if (val < 0x002) {
522 dev_err(&dev->pdev->dev, "too low clock rate (%lu Hz).\n",
523 clkrate);
524 return -EINVAL;
525 }
526
527 /* We have 12 bits clock divider only! */
528 if (val & 0xFFFFF000U) {
529 dev_err(&dev->pdev->dev, "too high clock rate (%lu Hz).\n",
530 clkrate);
531 return -EINVAL;
532 }
533
534 if (dev->speed > 100000) {
535 /* CC6..CC0 */
536 stu300_wr8((val & I2C_CCR_CC_MASK) | I2C_CCR_FMSM,
537 dev->virtbase + I2C_CCR);
538 dev_dbg(&dev->pdev->dev, "set clock divider to 0x%08x, "
539 "Fast Mode I2C\n", val);
540 } else {
541 /* CC6..CC0 */
542 stu300_wr8((val & I2C_CCR_CC_MASK),
543 dev->virtbase + I2C_CCR);
544 dev_dbg(&dev->pdev->dev, "set clock divider to "
545 "0x%08x, Standard Mode I2C\n", val);
546 }
547
548 /* CC11..CC7 */
549 stu300_wr8(((val >> 7) & 0x1F),
550 dev->virtbase + I2C_ECCR);
551
552 return 0;
553 }
554
555
stu300_init_hw(struct stu300_dev * dev)556 static int stu300_init_hw(struct stu300_dev *dev)
557 {
558 u32 dummy;
559 unsigned long clkrate;
560 int ret;
561
562 /* Disable controller */
563 stu300_wr8(0x00, dev->virtbase + I2C_CR);
564 /*
565 * Set own address to some default value (0x00).
566 * We do not support slave mode anyway.
567 */
568 stu300_wr8(0x00, dev->virtbase + I2C_OAR1);
569 /*
570 * The I2C controller only operates properly in 26 MHz but we
571 * program this driver as if we didn't know. This will also set the two
572 * high bits of the own address to zero as well.
573 * There is no known hardware issue with running in 13 MHz
574 * However, speeds over 200 kHz are not used.
575 */
576 clkrate = clk_get_rate(dev->clk);
577 ret = stu300_set_clk(dev, clkrate);
578
579 if (ret)
580 return ret;
581 /*
582 * Enable block, do it TWICE (hardware glitch)
583 * Setting bit 7 can enable DDC mode. (Not used currently.)
584 */
585 stu300_wr8(I2C_CR_PERIPHERAL_ENABLE,
586 dev->virtbase + I2C_CR);
587 stu300_wr8(I2C_CR_PERIPHERAL_ENABLE,
588 dev->virtbase + I2C_CR);
589 /* Make a dummy read of the status register SR1 & SR2 */
590 dummy = stu300_r8(dev->virtbase + I2C_SR2);
591 dummy = stu300_r8(dev->virtbase + I2C_SR1);
592
593 return 0;
594 }
595
596
597
598 /* Send slave address. */
stu300_send_address(struct stu300_dev * dev,struct i2c_msg * msg,int resend)599 static int stu300_send_address(struct stu300_dev *dev,
600 struct i2c_msg *msg, int resend)
601 {
602 u32 val;
603 int ret;
604
605 if (msg->flags & I2C_M_TEN)
606 /* This is probably how 10 bit addresses look */
607 val = (0xf0 | (((u32) msg->addr & 0x300) >> 7)) &
608 I2C_DR_D_MASK;
609 else
610 val = ((msg->addr << 1) & I2C_DR_D_MASK);
611
612 if (msg->flags & I2C_M_RD) {
613 /* This is the direction bit */
614 val |= 0x01;
615 if (resend)
616 dev_dbg(&dev->pdev->dev, "read resend\n");
617 } else if (resend)
618 dev_dbg(&dev->pdev->dev, "write resend\n");
619 stu300_wr8(val, dev->virtbase + I2C_DR);
620
621 /* For 10bit addressing, await 10bit request (EVENT 9) */
622 if (msg->flags & I2C_M_TEN) {
623 ret = stu300_await_event(dev, STU300_EVENT_9);
624 /*
625 * The slave device wants a 10bit address, send the rest
626 * of the bits (the LSBits)
627 */
628 val = msg->addr & I2C_DR_D_MASK;
629 /* This clears "event 9" */
630 stu300_wr8(val, dev->virtbase + I2C_DR);
631 if (ret != 0)
632 return ret;
633 }
634 /* FIXME: Why no else here? two events for 10bit?
635 * Await event 6 (normal) or event 9 (10bit)
636 */
637
638 if (resend)
639 dev_dbg(&dev->pdev->dev, "await event 6\n");
640 ret = stu300_await_event(dev, STU300_EVENT_6);
641
642 /*
643 * Clear any pending EVENT 6 no matter what happened during
644 * await_event.
645 */
646 val = stu300_r8(dev->virtbase + I2C_CR);
647 val |= I2C_CR_PERIPHERAL_ENABLE;
648 stu300_wr8(val, dev->virtbase + I2C_CR);
649
650 return ret;
651 }
652
stu300_xfer_msg(struct i2c_adapter * adap,struct i2c_msg * msg,int stop)653 static int stu300_xfer_msg(struct i2c_adapter *adap,
654 struct i2c_msg *msg, int stop)
655 {
656 u32 cr;
657 u32 val;
658 u32 i;
659 int ret;
660 int attempts = 0;
661 struct stu300_dev *dev = i2c_get_adapdata(adap);
662
663 clk_enable(dev->clk);
664
665 /* Remove this if (0) to trace each and every message. */
666 if (0) {
667 dev_dbg(&dev->pdev->dev, "I2C message to: 0x%04x, len: %d, "
668 "flags: 0x%04x, stop: %d\n",
669 msg->addr, msg->len, msg->flags, stop);
670 }
671
672 /* Zero-length messages are not supported by this hardware */
673 if (msg->len == 0) {
674 ret = -EINVAL;
675 goto exit_disable;
676 }
677
678 /*
679 * For some reason, sending the address sometimes fails when running
680 * on the 13 MHz clock. No interrupt arrives. This is a work around,
681 * which tries to restart and send the address up to 10 times before
682 * really giving up. Usually 5 to 8 attempts are enough.
683 */
684 do {
685 if (attempts)
686 dev_dbg(&dev->pdev->dev, "wait while busy\n");
687 /* Check that the bus is free, or wait until some timeout */
688 ret = stu300_wait_while_busy(dev);
689 if (ret != 0)
690 goto exit_disable;
691
692 if (attempts)
693 dev_dbg(&dev->pdev->dev, "re-int hw\n");
694 /*
695 * According to ST, there is no problem if the clock is
696 * changed between 13 and 26 MHz during a transfer.
697 */
698 ret = stu300_init_hw(dev);
699 if (ret)
700 goto exit_disable;
701
702 /* Send a start condition */
703 cr = I2C_CR_PERIPHERAL_ENABLE;
704 /* Setting the START bit puts the block in master mode */
705 if (!(msg->flags & I2C_M_NOSTART))
706 cr |= I2C_CR_START_ENABLE;
707 if ((msg->flags & I2C_M_RD) && (msg->len > 1))
708 /* On read more than 1 byte, we need ack. */
709 cr |= I2C_CR_ACK_ENABLE;
710 /* Check that it gets through */
711 if (!(msg->flags & I2C_M_NOSTART)) {
712 if (attempts)
713 dev_dbg(&dev->pdev->dev, "send start event\n");
714 ret = stu300_start_and_await_event(dev, cr,
715 STU300_EVENT_5);
716 }
717
718 if (attempts)
719 dev_dbg(&dev->pdev->dev, "send address\n");
720
721 if (ret == 0)
722 /* Send address */
723 ret = stu300_send_address(dev, msg, attempts != 0);
724
725 if (ret != 0) {
726 attempts++;
727 dev_dbg(&dev->pdev->dev, "failed sending address, "
728 "retrying. Attempt: %d msg_index: %d/%d\n",
729 attempts, dev->msg_index, dev->msg_len);
730 }
731
732 } while (ret != 0 && attempts < NUM_ADDR_RESEND_ATTEMPTS);
733
734 if (attempts < NUM_ADDR_RESEND_ATTEMPTS && attempts > 0) {
735 dev_dbg(&dev->pdev->dev, "managed to get address "
736 "through after %d attempts\n", attempts);
737 } else if (attempts == NUM_ADDR_RESEND_ATTEMPTS) {
738 dev_dbg(&dev->pdev->dev, "I give up, tried %d times "
739 "to resend address.\n",
740 NUM_ADDR_RESEND_ATTEMPTS);
741 goto exit_disable;
742 }
743
744
745 if (msg->flags & I2C_M_RD) {
746 /* READ: we read the actual bytes one at a time */
747 for (i = 0; i < msg->len; i++) {
748 if (i == msg->len-1) {
749 /*
750 * Disable ACK and set STOP condition before
751 * reading last byte
752 */
753 val = I2C_CR_PERIPHERAL_ENABLE;
754
755 if (stop)
756 val |= I2C_CR_STOP_ENABLE;
757
758 stu300_wr8(val,
759 dev->virtbase + I2C_CR);
760 }
761 /* Wait for this byte... */
762 ret = stu300_await_event(dev, STU300_EVENT_7);
763 if (ret != 0)
764 goto exit_disable;
765 /* This clears event 7 */
766 msg->buf[i] = (u8) stu300_r8(dev->virtbase + I2C_DR);
767 }
768 } else {
769 /* WRITE: we send the actual bytes one at a time */
770 for (i = 0; i < msg->len; i++) {
771 /* Write the byte */
772 stu300_wr8(msg->buf[i],
773 dev->virtbase + I2C_DR);
774 /* Check status */
775 ret = stu300_await_event(dev, STU300_EVENT_8);
776 /* Next write to DR will clear event 8 */
777 if (ret != 0) {
778 dev_err(&dev->pdev->dev, "error awaiting "
779 "event 8 (%d)\n", ret);
780 goto exit_disable;
781 }
782 }
783 /* Check NAK */
784 if (!(msg->flags & I2C_M_IGNORE_NAK)) {
785 if (stu300_r8(dev->virtbase + I2C_SR2) &
786 I2C_SR2_AF_IND) {
787 dev_err(&dev->pdev->dev, "I2C payload "
788 "send returned NAK!\n");
789 ret = -EIO;
790 goto exit_disable;
791 }
792 }
793 if (stop) {
794 /* Send stop condition */
795 val = I2C_CR_PERIPHERAL_ENABLE;
796 val |= I2C_CR_STOP_ENABLE;
797 stu300_wr8(val, dev->virtbase + I2C_CR);
798 }
799 }
800
801 /* Check that the bus is free, or wait until some timeout occurs */
802 ret = stu300_wait_while_busy(dev);
803 if (ret != 0) {
804 dev_err(&dev->pdev->dev, "timeout waiting for transfer "
805 "to commence.\n");
806 goto exit_disable;
807 }
808
809 /* Dummy read status registers */
810 val = stu300_r8(dev->virtbase + I2C_SR2);
811 val = stu300_r8(dev->virtbase + I2C_SR1);
812 ret = 0;
813
814 exit_disable:
815 /* Disable controller */
816 stu300_wr8(0x00, dev->virtbase + I2C_CR);
817 clk_disable(dev->clk);
818 return ret;
819 }
820
stu300_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)821 static int stu300_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
822 int num)
823 {
824 int ret = -1;
825 int i;
826
827 struct stu300_dev *dev = i2c_get_adapdata(adap);
828 dev->msg_len = num;
829
830 for (i = 0; i < num; i++) {
831 /*
832 * Another driver appears to send stop for each message,
833 * here we only do that for the last message. Possibly some
834 * peripherals require this behaviour, then their drivers
835 * have to send single messages in order to get "stop" for
836 * each message.
837 */
838 dev->msg_index = i;
839
840 ret = stu300_xfer_msg(adap, &msgs[i], (i == (num - 1)));
841
842 if (ret != 0) {
843 num = ret;
844 break;
845 }
846 }
847
848 return num;
849 }
850
stu300_func(struct i2c_adapter * adap)851 static u32 stu300_func(struct i2c_adapter *adap)
852 {
853 /* This is the simplest thing you can think of... */
854 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
855 }
856
857 static const struct i2c_algorithm stu300_algo = {
858 .master_xfer = stu300_xfer,
859 .functionality = stu300_func,
860 };
861
stu300_probe(struct platform_device * pdev)862 static int stu300_probe(struct platform_device *pdev)
863 {
864 struct stu300_dev *dev;
865 struct i2c_adapter *adap;
866 struct resource *res;
867 int bus_nr;
868 int ret = 0;
869
870 dev = devm_kzalloc(&pdev->dev, sizeof(struct stu300_dev), GFP_KERNEL);
871 if (!dev)
872 return -ENOMEM;
873
874 bus_nr = pdev->id;
875 dev->clk = devm_clk_get(&pdev->dev, NULL);
876 if (IS_ERR(dev->clk)) {
877 dev_err(&pdev->dev, "could not retrieve i2c bus clock\n");
878 return PTR_ERR(dev->clk);
879 }
880
881 dev->pdev = pdev;
882 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
883 dev->virtbase = devm_ioremap_resource(&pdev->dev, res);
884 dev_dbg(&pdev->dev, "initialize bus device I2C%d on virtual "
885 "base %p\n", bus_nr, dev->virtbase);
886 if (IS_ERR(dev->virtbase))
887 return PTR_ERR(dev->virtbase);
888
889 dev->irq = platform_get_irq(pdev, 0);
890 ret = devm_request_irq(&pdev->dev, dev->irq, stu300_irh, 0, NAME, dev);
891 if (ret < 0)
892 return ret;
893
894 dev->speed = scl_frequency;
895
896 clk_prepare_enable(dev->clk);
897 ret = stu300_init_hw(dev);
898 clk_disable(dev->clk);
899 if (ret != 0) {
900 dev_err(&dev->pdev->dev, "error initializing hardware.\n");
901 return -EIO;
902 }
903
904 /* IRQ event handling initialization */
905 spin_lock_init(&dev->cmd_issue_lock);
906 dev->cmd_event = STU300_EVENT_NONE;
907 dev->cmd_err = STU300_ERROR_NONE;
908
909 adap = &dev->adapter;
910 adap->owner = THIS_MODULE;
911 /* DDC class but actually often used for more generic I2C */
912 adap->class = I2C_CLASS_DEPRECATED;
913 strlcpy(adap->name, "ST Microelectronics DDC I2C adapter",
914 sizeof(adap->name));
915 adap->nr = bus_nr;
916 adap->algo = &stu300_algo;
917 adap->dev.parent = &pdev->dev;
918 adap->dev.of_node = pdev->dev.of_node;
919 i2c_set_adapdata(adap, dev);
920
921 /* i2c device drivers may be active on return from add_adapter() */
922 ret = i2c_add_numbered_adapter(adap);
923 if (ret)
924 return ret;
925
926 platform_set_drvdata(pdev, dev);
927 dev_info(&pdev->dev, "ST DDC I2C @ %p, irq %d\n",
928 dev->virtbase, dev->irq);
929
930 return 0;
931 }
932
933 #ifdef CONFIG_PM_SLEEP
stu300_suspend(struct device * device)934 static int stu300_suspend(struct device *device)
935 {
936 struct stu300_dev *dev = dev_get_drvdata(device);
937
938 /* Turn off everything */
939 stu300_wr8(0x00, dev->virtbase + I2C_CR);
940 return 0;
941 }
942
stu300_resume(struct device * device)943 static int stu300_resume(struct device *device)
944 {
945 int ret = 0;
946 struct stu300_dev *dev = dev_get_drvdata(device);
947
948 clk_enable(dev->clk);
949 ret = stu300_init_hw(dev);
950 clk_disable(dev->clk);
951
952 if (ret != 0)
953 dev_err(device, "error re-initializing hardware.\n");
954 return ret;
955 }
956
957 static SIMPLE_DEV_PM_OPS(stu300_pm, stu300_suspend, stu300_resume);
958 #define STU300_I2C_PM (&stu300_pm)
959 #else
960 #define STU300_I2C_PM NULL
961 #endif
962
stu300_remove(struct platform_device * pdev)963 static int stu300_remove(struct platform_device *pdev)
964 {
965 struct stu300_dev *dev = platform_get_drvdata(pdev);
966
967 i2c_del_adapter(&dev->adapter);
968 /* Turn off everything */
969 stu300_wr8(0x00, dev->virtbase + I2C_CR);
970 return 0;
971 }
972
973 static const struct of_device_id stu300_dt_match[] = {
974 { .compatible = "st,ddci2c" },
975 {},
976 };
977 MODULE_DEVICE_TABLE(of, stu300_dt_match);
978
979 static struct platform_driver stu300_i2c_driver = {
980 .driver = {
981 .name = NAME,
982 .pm = STU300_I2C_PM,
983 .of_match_table = stu300_dt_match,
984 },
985 .probe = stu300_probe,
986 .remove = stu300_remove,
987
988 };
989
stu300_init(void)990 static int __init stu300_init(void)
991 {
992 return platform_driver_register(&stu300_i2c_driver);
993 }
994
stu300_exit(void)995 static void __exit stu300_exit(void)
996 {
997 platform_driver_unregister(&stu300_i2c_driver);
998 }
999
1000 /*
1001 * The systems using this bus often have very basic devices such
1002 * as regulators on the I2C bus, so this needs to be loaded early.
1003 * Therefore it is registered in the subsys_initcall().
1004 */
1005 subsys_initcall(stu300_init);
1006 module_exit(stu300_exit);
1007
1008 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
1009 MODULE_DESCRIPTION("ST Micro DDC I2C adapter (" NAME ")");
1010 MODULE_LICENSE("GPL");
1011 MODULE_ALIAS("platform:" NAME);
1012