1 /* 2 * Copyright (C) 2012 Invensense, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 #include <linux/i2c.h> 14 #include <linux/i2c-mux.h> 15 #include <linux/kfifo.h> 16 #include <linux/spinlock.h> 17 #include <linux/iio/iio.h> 18 #include <linux/iio/buffer.h> 19 #include <linux/regmap.h> 20 #include <linux/iio/sysfs.h> 21 #include <linux/iio/kfifo_buf.h> 22 #include <linux/iio/trigger.h> 23 #include <linux/iio/triggered_buffer.h> 24 #include <linux/iio/trigger_consumer.h> 25 #include <linux/platform_data/invensense_mpu6050.h> 26 27 /** 28 * struct inv_mpu6050_reg_map - Notable registers. 29 * @sample_rate_div: Divider applied to gyro output rate. 30 * @lpf: Configures internal low pass filter. 31 * @accel_lpf: Configures accelerometer low pass filter. 32 * @user_ctrl: Enables/resets the FIFO. 33 * @fifo_en: Determines which data will appear in FIFO. 34 * @gyro_config: gyro config register. 35 * @accl_config: accel config register 36 * @fifo_count_h: Upper byte of FIFO count. 37 * @fifo_r_w: FIFO register. 38 * @raw_gyro: Address of first gyro register. 39 * @raw_accl: Address of first accel register. 40 * @temperature: temperature register 41 * @int_enable: Interrupt enable register. 42 * @pwr_mgmt_1: Controls chip's power state and clock source. 43 * @pwr_mgmt_2: Controls power state of individual sensors. 44 * @int_pin_cfg; Controls interrupt pin configuration. 45 * @accl_offset: Controls the accelerometer calibration offset. 46 * @gyro_offset: Controls the gyroscope calibration offset. 47 */ 48 struct inv_mpu6050_reg_map { 49 u8 sample_rate_div; 50 u8 lpf; 51 u8 accel_lpf; 52 u8 user_ctrl; 53 u8 fifo_en; 54 u8 gyro_config; 55 u8 accl_config; 56 u8 fifo_count_h; 57 u8 fifo_r_w; 58 u8 raw_gyro; 59 u8 raw_accl; 60 u8 temperature; 61 u8 int_enable; 62 u8 pwr_mgmt_1; 63 u8 pwr_mgmt_2; 64 u8 int_pin_cfg; 65 u8 accl_offset; 66 u8 gyro_offset; 67 }; 68 69 /*device enum */ 70 enum inv_devices { 71 INV_MPU6050, 72 INV_MPU6500, 73 INV_MPU6000, 74 INV_MPU9150, 75 INV_ICM20608, 76 INV_NUM_PARTS 77 }; 78 79 /** 80 * struct inv_mpu6050_chip_config - Cached chip configuration data. 81 * @fsr: Full scale range. 82 * @lpf: Digital low pass filter frequency. 83 * @accl_fs: accel full scale range. 84 * @enable: master enable state. 85 * @accl_fifo_enable: enable accel data output 86 * @gyro_fifo_enable: enable gyro data output 87 * @fifo_rate: FIFO update rate. 88 */ 89 struct inv_mpu6050_chip_config { 90 unsigned int fsr:2; 91 unsigned int lpf:3; 92 unsigned int accl_fs:2; 93 unsigned int enable:1; 94 unsigned int accl_fifo_enable:1; 95 unsigned int gyro_fifo_enable:1; 96 u16 fifo_rate; 97 }; 98 99 /** 100 * struct inv_mpu6050_hw - Other important hardware information. 101 * @whoami: Self identification byte from WHO_AM_I register 102 * @name: name of the chip. 103 * @reg: register map of the chip. 104 * @config: configuration of the chip. 105 */ 106 struct inv_mpu6050_hw { 107 u8 whoami; 108 u8 *name; 109 const struct inv_mpu6050_reg_map *reg; 110 const struct inv_mpu6050_chip_config *config; 111 }; 112 113 /* 114 * struct inv_mpu6050_state - Driver state variables. 115 * @TIMESTAMP_FIFO_SIZE: fifo size for timestamp. 116 * @trig: IIO trigger. 117 * @chip_config: Cached attribute information. 118 * @reg: Map of important registers. 119 * @hw: Other hardware-specific information. 120 * @chip_type: chip type. 121 * @time_stamp_lock: spin lock to time stamp. 122 * @plat_data: platform data (deprecated in favor of @orientation). 123 * @orientation: sensor chip orientation relative to main hardware. 124 * @timestamps: kfifo queue to store time stamp. 125 * @map regmap pointer. 126 * @irq interrupt number. 127 */ 128 struct inv_mpu6050_state { 129 #define TIMESTAMP_FIFO_SIZE 16 130 struct iio_trigger *trig; 131 struct inv_mpu6050_chip_config chip_config; 132 const struct inv_mpu6050_reg_map *reg; 133 const struct inv_mpu6050_hw *hw; 134 enum inv_devices chip_type; 135 spinlock_t time_stamp_lock; 136 struct i2c_mux_core *muxc; 137 struct i2c_client *mux_client; 138 unsigned int powerup_count; 139 struct inv_mpu6050_platform_data plat_data; 140 struct iio_mount_matrix orientation; 141 DECLARE_KFIFO(timestamps, long long, TIMESTAMP_FIFO_SIZE); 142 struct regmap *map; 143 int irq; 144 }; 145 146 /*register and associated bit definition*/ 147 #define INV_MPU6050_REG_ACCEL_OFFSET 0x06 148 #define INV_MPU6050_REG_GYRO_OFFSET 0x13 149 150 #define INV_MPU6050_REG_SAMPLE_RATE_DIV 0x19 151 #define INV_MPU6050_REG_CONFIG 0x1A 152 #define INV_MPU6050_REG_GYRO_CONFIG 0x1B 153 #define INV_MPU6050_REG_ACCEL_CONFIG 0x1C 154 155 #define INV_MPU6050_REG_FIFO_EN 0x23 156 #define INV_MPU6050_BIT_ACCEL_OUT 0x08 157 #define INV_MPU6050_BITS_GYRO_OUT 0x70 158 159 #define INV_MPU6050_REG_INT_ENABLE 0x38 160 #define INV_MPU6050_BIT_DATA_RDY_EN 0x01 161 #define INV_MPU6050_BIT_DMP_INT_EN 0x02 162 163 #define INV_MPU6050_REG_RAW_ACCEL 0x3B 164 #define INV_MPU6050_REG_TEMPERATURE 0x41 165 #define INV_MPU6050_REG_RAW_GYRO 0x43 166 167 #define INV_MPU6050_REG_USER_CTRL 0x6A 168 #define INV_MPU6050_BIT_FIFO_RST 0x04 169 #define INV_MPU6050_BIT_DMP_RST 0x08 170 #define INV_MPU6050_BIT_I2C_MST_EN 0x20 171 #define INV_MPU6050_BIT_FIFO_EN 0x40 172 #define INV_MPU6050_BIT_DMP_EN 0x80 173 #define INV_MPU6050_BIT_I2C_IF_DIS 0x10 174 175 #define INV_MPU6050_REG_PWR_MGMT_1 0x6B 176 #define INV_MPU6050_BIT_H_RESET 0x80 177 #define INV_MPU6050_BIT_SLEEP 0x40 178 #define INV_MPU6050_BIT_CLK_MASK 0x7 179 180 #define INV_MPU6050_REG_PWR_MGMT_2 0x6C 181 #define INV_MPU6050_BIT_PWR_ACCL_STBY 0x38 182 #define INV_MPU6050_BIT_PWR_GYRO_STBY 0x07 183 184 #define INV_MPU6050_REG_FIFO_COUNT_H 0x72 185 #define INV_MPU6050_REG_FIFO_R_W 0x74 186 187 #define INV_MPU6050_BYTES_PER_3AXIS_SENSOR 6 188 #define INV_MPU6050_FIFO_COUNT_BYTE 2 189 #define INV_MPU6050_FIFO_THRESHOLD 500 190 191 /* mpu6500 registers */ 192 #define INV_MPU6500_REG_ACCEL_CONFIG_2 0x1D 193 #define INV_MPU6500_REG_ACCEL_OFFSET 0x77 194 195 /* delay time in milliseconds */ 196 #define INV_MPU6050_POWER_UP_TIME 100 197 #define INV_MPU6050_TEMP_UP_TIME 100 198 #define INV_MPU6050_SENSOR_UP_TIME 30 199 200 /* delay time in microseconds */ 201 #define INV_MPU6050_REG_UP_TIME_MIN 5000 202 #define INV_MPU6050_REG_UP_TIME_MAX 10000 203 204 #define INV_MPU6050_TEMP_OFFSET 12421 205 #define INV_MPU6050_TEMP_SCALE 2941 206 #define INV_MPU6050_MAX_GYRO_FS_PARAM 3 207 #define INV_MPU6050_MAX_ACCL_FS_PARAM 3 208 #define INV_MPU6050_THREE_AXIS 3 209 #define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT 3 210 #define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT 3 211 212 /* 6 + 6 round up and plus 8 */ 213 #define INV_MPU6050_OUTPUT_DATA_SIZE 24 214 215 #define INV_MPU6050_REG_INT_PIN_CFG 0x37 216 #define INV_MPU6050_BIT_BYPASS_EN 0x2 217 #define INV_MPU6050_INT_PIN_CFG 0 218 219 /* init parameters */ 220 #define INV_MPU6050_INIT_FIFO_RATE 50 221 #define INV_MPU6050_TIME_STAMP_TOR 5 222 #define INV_MPU6050_MAX_FIFO_RATE 1000 223 #define INV_MPU6050_MIN_FIFO_RATE 4 224 #define INV_MPU6050_ONE_K_HZ 1000 225 226 #define INV_MPU6050_REG_WHOAMI 117 227 228 #define INV_MPU6000_WHOAMI_VALUE 0x68 229 #define INV_MPU6050_WHOAMI_VALUE 0x68 230 #define INV_MPU6500_WHOAMI_VALUE 0x70 231 #define INV_MPU9150_WHOAMI_VALUE 0x68 232 #define INV_ICM20608_WHOAMI_VALUE 0xAF 233 234 /* scan element definition */ 235 enum inv_mpu6050_scan { 236 INV_MPU6050_SCAN_ACCL_X, 237 INV_MPU6050_SCAN_ACCL_Y, 238 INV_MPU6050_SCAN_ACCL_Z, 239 INV_MPU6050_SCAN_GYRO_X, 240 INV_MPU6050_SCAN_GYRO_Y, 241 INV_MPU6050_SCAN_GYRO_Z, 242 INV_MPU6050_SCAN_TIMESTAMP, 243 }; 244 245 enum inv_mpu6050_filter_e { 246 INV_MPU6050_FILTER_256HZ_NOLPF2 = 0, 247 INV_MPU6050_FILTER_188HZ, 248 INV_MPU6050_FILTER_98HZ, 249 INV_MPU6050_FILTER_42HZ, 250 INV_MPU6050_FILTER_20HZ, 251 INV_MPU6050_FILTER_10HZ, 252 INV_MPU6050_FILTER_5HZ, 253 INV_MPU6050_FILTER_2100HZ_NOLPF, 254 NUM_MPU6050_FILTER 255 }; 256 257 /* IIO attribute address */ 258 enum INV_MPU6050_IIO_ATTR_ADDR { 259 ATTR_GYRO_MATRIX, 260 ATTR_ACCL_MATRIX, 261 }; 262 263 enum inv_mpu6050_accl_fs_e { 264 INV_MPU6050_FS_02G = 0, 265 INV_MPU6050_FS_04G, 266 INV_MPU6050_FS_08G, 267 INV_MPU6050_FS_16G, 268 NUM_ACCL_FSR 269 }; 270 271 enum inv_mpu6050_fsr_e { 272 INV_MPU6050_FSR_250DPS = 0, 273 INV_MPU6050_FSR_500DPS, 274 INV_MPU6050_FSR_1000DPS, 275 INV_MPU6050_FSR_2000DPS, 276 NUM_MPU6050_FSR 277 }; 278 279 enum inv_mpu6050_clock_sel_e { 280 INV_CLK_INTERNAL = 0, 281 INV_CLK_PLL, 282 NUM_CLK 283 }; 284 285 irqreturn_t inv_mpu6050_irq_handler(int irq, void *p); 286 irqreturn_t inv_mpu6050_read_fifo(int irq, void *p); 287 int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev); 288 void inv_mpu6050_remove_trigger(struct inv_mpu6050_state *st); 289 int inv_reset_fifo(struct iio_dev *indio_dev); 290 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask); 291 int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val); 292 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on); 293 int inv_mpu_acpi_create_mux_client(struct i2c_client *client); 294 void inv_mpu_acpi_delete_mux_client(struct i2c_client *client); 295 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name, 296 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type); 297 int inv_mpu_core_remove(struct device *dev); 298 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on); 299 extern const struct dev_pm_ops inv_mpu_pmops; 300