1 /*
2 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/irq.h>
20 #include <linux/irqchip/arm-gic.h>
21
22 #include "irq-gic-common.h"
23
24 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
25
26 static const struct gic_kvm_info *gic_kvm_info;
27
gic_get_kvm_info(void)28 const struct gic_kvm_info *gic_get_kvm_info(void)
29 {
30 return gic_kvm_info;
31 }
32
gic_set_kvm_info(const struct gic_kvm_info * info)33 void gic_set_kvm_info(const struct gic_kvm_info *info)
34 {
35 BUG_ON(gic_kvm_info != NULL);
36 gic_kvm_info = info;
37 }
38
gic_enable_quirks(u32 iidr,const struct gic_quirk * quirks,void * data)39 void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks,
40 void *data)
41 {
42 for (; quirks->desc; quirks++) {
43 if (quirks->iidr != (quirks->mask & iidr))
44 continue;
45 quirks->init(data);
46 pr_info("GIC: enabling workaround for %s\n", quirks->desc);
47 }
48 }
49
gic_configure_irq(unsigned int irq,unsigned int type,void __iomem * base,void (* sync_access)(void))50 int gic_configure_irq(unsigned int irq, unsigned int type,
51 void __iomem *base, void (*sync_access)(void))
52 {
53 u32 confmask = 0x2 << ((irq % 16) * 2);
54 u32 confoff = (irq / 16) * 4;
55 u32 val, oldval;
56 int ret = 0;
57 unsigned long flags;
58
59 /*
60 * Read current configuration register, and insert the config
61 * for "irq", depending on "type".
62 */
63 raw_spin_lock_irqsave(&irq_controller_lock, flags);
64 val = oldval = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
65 if (type & IRQ_TYPE_LEVEL_MASK)
66 val &= ~confmask;
67 else if (type & IRQ_TYPE_EDGE_BOTH)
68 val |= confmask;
69
70 /* If the current configuration is the same, then we are done */
71 if (val == oldval) {
72 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
73 return 0;
74 }
75
76 /*
77 * Write back the new configuration, and possibly re-enable
78 * the interrupt. If we fail to write a new configuration for
79 * an SPI then WARN and return an error. If we fail to write the
80 * configuration for a PPI this is most likely because the GIC
81 * does not allow us to set the configuration or we are in a
82 * non-secure mode, and hence it may not be catastrophic.
83 */
84 writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
85 if (readl_relaxed(base + GIC_DIST_CONFIG + confoff) != val) {
86 if (WARN_ON(irq >= 32))
87 ret = -EINVAL;
88 else
89 pr_warn("GIC: PPI%d is secure or misconfigured\n",
90 irq - 16);
91 }
92 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
93
94 if (sync_access)
95 sync_access();
96
97 return ret;
98 }
99
gic_dist_config(void __iomem * base,int gic_irqs,void (* sync_access)(void))100 void gic_dist_config(void __iomem *base, int gic_irqs,
101 void (*sync_access)(void))
102 {
103 unsigned int i;
104
105 /*
106 * Set all global interrupts to be level triggered, active low.
107 */
108 for (i = 32; i < gic_irqs; i += 16)
109 writel_relaxed(GICD_INT_ACTLOW_LVLTRIG,
110 base + GIC_DIST_CONFIG + i / 4);
111
112 /*
113 * Set priority on all global interrupts.
114 */
115 for (i = 32; i < gic_irqs; i += 4)
116 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i);
117
118 /*
119 * Deactivate and disable all SPIs. Leave the PPI and SGIs
120 * alone as they are in the redistributor registers on GICv3.
121 */
122 for (i = 32; i < gic_irqs; i += 32) {
123 writel_relaxed(GICD_INT_EN_CLR_X32,
124 base + GIC_DIST_ACTIVE_CLEAR + i / 8);
125 writel_relaxed(GICD_INT_EN_CLR_X32,
126 base + GIC_DIST_ENABLE_CLEAR + i / 8);
127 }
128
129 if (sync_access)
130 sync_access();
131 }
132
gic_cpu_config(void __iomem * base,void (* sync_access)(void))133 void gic_cpu_config(void __iomem *base, void (*sync_access)(void))
134 {
135 int i;
136
137 /*
138 * Deal with the banked PPI and SGI interrupts - disable all
139 * PPI interrupts, ensure all SGI interrupts are enabled.
140 * Make sure everything is deactivated.
141 */
142 writel_relaxed(GICD_INT_EN_CLR_X32, base + GIC_DIST_ACTIVE_CLEAR);
143 writel_relaxed(GICD_INT_EN_CLR_PPI, base + GIC_DIST_ENABLE_CLEAR);
144 writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET);
145
146 /*
147 * Set priority on PPI and SGI interrupts
148 */
149 for (i = 0; i < 32; i += 4)
150 writel_relaxed(GICD_INT_DEF_PRI_X4,
151 base + GIC_DIST_PRI + i * 4 / 4);
152
153 if (sync_access)
154 sync_access();
155 }
156