1 /*
2 * arch/arm/mach-vt8500/irq.c
3 *
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 /*
23 * This file is copied and modified from the original irq.c provided by
24 * Alexey Charkov. Minor changes have been made for Device Tree Support.
25 */
26
27 #include <linux/slab.h>
28 #include <linux/io.h>
29 #include <linux/irq.h>
30 #include <linux/irqchip.h>
31 #include <linux/irqdomain.h>
32 #include <linux/interrupt.h>
33 #include <linux/bitops.h>
34
35 #include <linux/of.h>
36 #include <linux/of_irq.h>
37 #include <linux/of_address.h>
38
39 #include <asm/irq.h>
40 #include <asm/exception.h>
41 #include <asm/mach/irq.h>
42
43 #define VT8500_ICPC_IRQ 0x20
44 #define VT8500_ICPC_FIQ 0x24
45 #define VT8500_ICDC 0x40 /* Destination Control 64*u32 */
46 #define VT8500_ICIS 0x80 /* Interrupt status, 16*u32 */
47
48 /* ICPC */
49 #define ICPC_MASK 0x3F
50 #define ICPC_ROTATE BIT(6)
51
52 /* IC_DCTR */
53 #define ICDC_IRQ 0x00
54 #define ICDC_FIQ 0x01
55 #define ICDC_DSS0 0x02
56 #define ICDC_DSS1 0x03
57 #define ICDC_DSS2 0x04
58 #define ICDC_DSS3 0x05
59 #define ICDC_DSS4 0x06
60 #define ICDC_DSS5 0x07
61
62 #define VT8500_INT_DISABLE 0
63 #define VT8500_INT_ENABLE BIT(3)
64
65 #define VT8500_TRIGGER_HIGH 0
66 #define VT8500_TRIGGER_RISING BIT(5)
67 #define VT8500_TRIGGER_FALLING BIT(6)
68 #define VT8500_EDGE ( VT8500_TRIGGER_RISING \
69 | VT8500_TRIGGER_FALLING)
70
71 /* vt8500 has 1 intc, wm8505 and wm8650 have 2 */
72 #define VT8500_INTC_MAX 2
73
74 struct vt8500_irq_data {
75 void __iomem *base; /* IO Memory base address */
76 struct irq_domain *domain; /* Domain for this controller */
77 };
78
79 /* Global variable for accessing io-mem addresses */
80 static struct vt8500_irq_data intc[VT8500_INTC_MAX];
81 static u32 active_cnt = 0;
82
vt8500_irq_mask(struct irq_data * d)83 static void vt8500_irq_mask(struct irq_data *d)
84 {
85 struct vt8500_irq_data *priv = d->domain->host_data;
86 void __iomem *base = priv->base;
87 void __iomem *stat_reg = base + VT8500_ICIS + (d->hwirq < 32 ? 0 : 4);
88 u8 edge, dctr;
89 u32 status;
90
91 edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE;
92 if (edge) {
93 status = readl(stat_reg);
94
95 status |= (1 << (d->hwirq & 0x1f));
96 writel(status, stat_reg);
97 } else {
98 dctr = readb(base + VT8500_ICDC + d->hwirq);
99 dctr &= ~VT8500_INT_ENABLE;
100 writeb(dctr, base + VT8500_ICDC + d->hwirq);
101 }
102 }
103
vt8500_irq_unmask(struct irq_data * d)104 static void vt8500_irq_unmask(struct irq_data *d)
105 {
106 struct vt8500_irq_data *priv = d->domain->host_data;
107 void __iomem *base = priv->base;
108 u8 dctr;
109
110 dctr = readb(base + VT8500_ICDC + d->hwirq);
111 dctr |= VT8500_INT_ENABLE;
112 writeb(dctr, base + VT8500_ICDC + d->hwirq);
113 }
114
vt8500_irq_set_type(struct irq_data * d,unsigned int flow_type)115 static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
116 {
117 struct vt8500_irq_data *priv = d->domain->host_data;
118 void __iomem *base = priv->base;
119 u8 dctr;
120
121 dctr = readb(base + VT8500_ICDC + d->hwirq);
122 dctr &= ~VT8500_EDGE;
123
124 switch (flow_type) {
125 case IRQF_TRIGGER_LOW:
126 return -EINVAL;
127 case IRQF_TRIGGER_HIGH:
128 dctr |= VT8500_TRIGGER_HIGH;
129 irq_set_handler_locked(d, handle_level_irq);
130 break;
131 case IRQF_TRIGGER_FALLING:
132 dctr |= VT8500_TRIGGER_FALLING;
133 irq_set_handler_locked(d, handle_edge_irq);
134 break;
135 case IRQF_TRIGGER_RISING:
136 dctr |= VT8500_TRIGGER_RISING;
137 irq_set_handler_locked(d, handle_edge_irq);
138 break;
139 }
140 writeb(dctr, base + VT8500_ICDC + d->hwirq);
141
142 return 0;
143 }
144
145 static struct irq_chip vt8500_irq_chip = {
146 .name = "vt8500",
147 .irq_ack = vt8500_irq_mask,
148 .irq_mask = vt8500_irq_mask,
149 .irq_unmask = vt8500_irq_unmask,
150 .irq_set_type = vt8500_irq_set_type,
151 };
152
vt8500_init_irq_hw(void __iomem * base)153 static void __init vt8500_init_irq_hw(void __iomem *base)
154 {
155 u32 i;
156
157 /* Enable rotating priority for IRQ */
158 writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ);
159 writel(0x00, base + VT8500_ICPC_FIQ);
160
161 /* Disable all interrupts and route them to IRQ */
162 for (i = 0; i < 64; i++)
163 writeb(VT8500_INT_DISABLE | ICDC_IRQ, base + VT8500_ICDC + i);
164 }
165
vt8500_irq_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw)166 static int vt8500_irq_map(struct irq_domain *h, unsigned int virq,
167 irq_hw_number_t hw)
168 {
169 irq_set_chip_and_handler(virq, &vt8500_irq_chip, handle_level_irq);
170
171 return 0;
172 }
173
174 static const struct irq_domain_ops vt8500_irq_domain_ops = {
175 .map = vt8500_irq_map,
176 .xlate = irq_domain_xlate_onecell,
177 };
178
vt8500_handle_irq(struct pt_regs * regs)179 static void __exception_irq_entry vt8500_handle_irq(struct pt_regs *regs)
180 {
181 u32 stat, i;
182 int irqnr;
183 void __iomem *base;
184
185 /* Loop through each active controller */
186 for (i=0; i<active_cnt; i++) {
187 base = intc[i].base;
188 irqnr = readl_relaxed(base) & 0x3F;
189 /*
190 Highest Priority register default = 63, so check that this
191 is a real interrupt by checking the status register
192 */
193 if (irqnr == 63) {
194 stat = readl_relaxed(base + VT8500_ICIS + 4);
195 if (!(stat & BIT(31)))
196 continue;
197 }
198
199 handle_domain_irq(intc[i].domain, irqnr, regs);
200 }
201 }
202
vt8500_irq_init(struct device_node * node,struct device_node * parent)203 static int __init vt8500_irq_init(struct device_node *node,
204 struct device_node *parent)
205 {
206 int irq, i;
207 struct device_node *np = node;
208
209 if (active_cnt == VT8500_INTC_MAX) {
210 pr_err("%s: Interrupt controllers > VT8500_INTC_MAX\n",
211 __func__);
212 goto out;
213 }
214
215 intc[active_cnt].base = of_iomap(np, 0);
216 intc[active_cnt].domain = irq_domain_add_linear(node, 64,
217 &vt8500_irq_domain_ops, &intc[active_cnt]);
218
219 if (!intc[active_cnt].base) {
220 pr_err("%s: Unable to map IO memory\n", __func__);
221 goto out;
222 }
223
224 if (!intc[active_cnt].domain) {
225 pr_err("%s: Unable to add irq domain!\n", __func__);
226 goto out;
227 }
228
229 set_handle_irq(vt8500_handle_irq);
230
231 vt8500_init_irq_hw(intc[active_cnt].base);
232
233 pr_info("vt8500-irq: Added interrupt controller\n");
234
235 active_cnt++;
236
237 /* check if this is a slaved controller */
238 if (of_irq_count(np) != 0) {
239 /* check that we have the correct number of interrupts */
240 if (of_irq_count(np) != 8) {
241 pr_err("%s: Incorrect IRQ map for slaved controller\n",
242 __func__);
243 return -EINVAL;
244 }
245
246 for (i = 0; i < 8; i++) {
247 irq = irq_of_parse_and_map(np, i);
248 enable_irq(irq);
249 }
250
251 pr_info("vt8500-irq: Enabled slave->parent interrupts\n");
252 }
253 out:
254 return 0;
255 }
256
257 IRQCHIP_DECLARE(vt8500_irq, "via,vt8500-intc", vt8500_irq_init);
258