1 /*
2 * Copyright (C) 2012 Stefan Roese <sr@denx.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10 #include <linux/device.h>
11 #include <linux/firmware.h>
12 #include <linux/module.h>
13 #include <linux/errno.h>
14 #include <linux/kernel.h>
15 #include <linux/spi/spi.h>
16 #include <linux/platform_device.h>
17 #include <linux/delay.h>
18 #include <asm/unaligned.h>
19
20 #define FIRMWARE_NAME "lattice-ecp3.bit"
21
22 /*
23 * The JTAG ID's of the supported FPGA's. The ID is 32bit wide
24 * reversed as noted in the manual.
25 */
26 #define ID_ECP3_17 0xc2088080
27 #define ID_ECP3_35 0xc2048080
28
29 /* FPGA commands */
30 #define FPGA_CMD_READ_ID 0x07 /* plus 24 bits */
31 #define FPGA_CMD_READ_STATUS 0x09 /* plus 24 bits */
32 #define FPGA_CMD_CLEAR 0x70
33 #define FPGA_CMD_REFRESH 0x71
34 #define FPGA_CMD_WRITE_EN 0x4a /* plus 2 bits */
35 #define FPGA_CMD_WRITE_DIS 0x4f /* plus 8 bits */
36 #define FPGA_CMD_WRITE_INC 0x41 /* plus 0 bits */
37
38 /*
39 * The status register is 32bit revered, DONE is bit 17 from the TN1222.pdf
40 * (LatticeECP3 Slave SPI Port User's Guide)
41 */
42 #define FPGA_STATUS_DONE 0x00004000
43 #define FPGA_STATUS_CLEARED 0x00010000
44
45 #define FPGA_CLEAR_TIMEOUT 5000 /* max. 5000ms for FPGA clear */
46 #define FPGA_CLEAR_MSLEEP 10
47 #define FPGA_CLEAR_LOOP_COUNT (FPGA_CLEAR_TIMEOUT / FPGA_CLEAR_MSLEEP)
48
49 struct fpga_data {
50 struct completion fw_loaded;
51 };
52
53 struct ecp3_dev {
54 u32 jedec_id;
55 char *name;
56 };
57
58 static const struct ecp3_dev ecp3_dev[] = {
59 {
60 .jedec_id = ID_ECP3_17,
61 .name = "Lattice ECP3-17",
62 },
63 {
64 .jedec_id = ID_ECP3_35,
65 .name = "Lattice ECP3-35",
66 },
67 };
68
firmware_load(const struct firmware * fw,void * context)69 static void firmware_load(const struct firmware *fw, void *context)
70 {
71 struct spi_device *spi = (struct spi_device *)context;
72 struct fpga_data *data = spi_get_drvdata(spi);
73 u8 *buffer;
74 int ret;
75 u8 txbuf[8];
76 u8 rxbuf[8];
77 int rx_len = 8;
78 int i;
79 u32 jedec_id;
80 u32 status;
81
82 if (fw == NULL) {
83 dev_err(&spi->dev, "Cannot load firmware, aborting\n");
84 return;
85 }
86
87 if (fw->size == 0) {
88 dev_err(&spi->dev, "Error: Firmware size is 0!\n");
89 return;
90 }
91
92 /* Fill dummy data (24 stuffing bits for commands) */
93 txbuf[1] = 0x00;
94 txbuf[2] = 0x00;
95 txbuf[3] = 0x00;
96
97 /* Trying to speak with the FPGA via SPI... */
98 txbuf[0] = FPGA_CMD_READ_ID;
99 ret = spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
100 jedec_id = get_unaligned_be32(&rxbuf[4]);
101 dev_dbg(&spi->dev, "FPGA JTAG ID=%08x\n", jedec_id);
102
103 for (i = 0; i < ARRAY_SIZE(ecp3_dev); i++) {
104 if (jedec_id == ecp3_dev[i].jedec_id)
105 break;
106 }
107 if (i == ARRAY_SIZE(ecp3_dev)) {
108 dev_err(&spi->dev,
109 "Error: No supported FPGA detected (JEDEC_ID=%08x)!\n",
110 jedec_id);
111 return;
112 }
113
114 dev_info(&spi->dev, "FPGA %s detected\n", ecp3_dev[i].name);
115
116 txbuf[0] = FPGA_CMD_READ_STATUS;
117 ret = spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
118 status = get_unaligned_be32(&rxbuf[4]);
119 dev_dbg(&spi->dev, "FPGA Status=%08x\n", status);
120
121 buffer = kzalloc(fw->size + 8, GFP_KERNEL);
122 if (!buffer) {
123 dev_err(&spi->dev, "Error: Can't allocate memory!\n");
124 return;
125 }
126
127 /*
128 * Insert WRITE_INC command into stream (one SPI frame)
129 */
130 buffer[0] = FPGA_CMD_WRITE_INC;
131 buffer[1] = 0xff;
132 buffer[2] = 0xff;
133 buffer[3] = 0xff;
134 memcpy(buffer + 4, fw->data, fw->size);
135
136 txbuf[0] = FPGA_CMD_REFRESH;
137 ret = spi_write(spi, txbuf, 4);
138
139 txbuf[0] = FPGA_CMD_WRITE_EN;
140 ret = spi_write(spi, txbuf, 4);
141
142 txbuf[0] = FPGA_CMD_CLEAR;
143 ret = spi_write(spi, txbuf, 4);
144
145 /*
146 * Wait for FPGA memory to become cleared
147 */
148 for (i = 0; i < FPGA_CLEAR_LOOP_COUNT; i++) {
149 txbuf[0] = FPGA_CMD_READ_STATUS;
150 ret = spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
151 status = get_unaligned_be32(&rxbuf[4]);
152 if (status == FPGA_STATUS_CLEARED)
153 break;
154
155 msleep(FPGA_CLEAR_MSLEEP);
156 }
157
158 if (i == FPGA_CLEAR_LOOP_COUNT) {
159 dev_err(&spi->dev,
160 "Error: Timeout waiting for FPGA to clear (status=%08x)!\n",
161 status);
162 kfree(buffer);
163 return;
164 }
165
166 dev_info(&spi->dev, "Configuring the FPGA...\n");
167 ret = spi_write(spi, buffer, fw->size + 8);
168
169 txbuf[0] = FPGA_CMD_WRITE_DIS;
170 ret = spi_write(spi, txbuf, 4);
171
172 txbuf[0] = FPGA_CMD_READ_STATUS;
173 ret = spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
174 status = get_unaligned_be32(&rxbuf[4]);
175 dev_dbg(&spi->dev, "FPGA Status=%08x\n", status);
176
177 /* Check result */
178 if (status & FPGA_STATUS_DONE)
179 dev_info(&spi->dev, "FPGA successfully configured!\n");
180 else
181 dev_info(&spi->dev, "FPGA not configured (DONE not set)\n");
182
183 /*
184 * Don't forget to release the firmware again
185 */
186 release_firmware(fw);
187
188 kfree(buffer);
189
190 complete(&data->fw_loaded);
191 }
192
lattice_ecp3_probe(struct spi_device * spi)193 static int lattice_ecp3_probe(struct spi_device *spi)
194 {
195 struct fpga_data *data;
196 int err;
197
198 data = devm_kzalloc(&spi->dev, sizeof(*data), GFP_KERNEL);
199 if (!data) {
200 dev_err(&spi->dev, "Memory allocation for fpga_data failed\n");
201 return -ENOMEM;
202 }
203 spi_set_drvdata(spi, data);
204
205 init_completion(&data->fw_loaded);
206 err = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
207 FIRMWARE_NAME, &spi->dev,
208 GFP_KERNEL, spi, firmware_load);
209 if (err) {
210 dev_err(&spi->dev, "Firmware loading failed with %d!\n", err);
211 return err;
212 }
213
214 dev_info(&spi->dev, "FPGA bitstream configuration driver registered\n");
215
216 return 0;
217 }
218
lattice_ecp3_remove(struct spi_device * spi)219 static int lattice_ecp3_remove(struct spi_device *spi)
220 {
221 struct fpga_data *data = spi_get_drvdata(spi);
222
223 wait_for_completion(&data->fw_loaded);
224
225 return 0;
226 }
227
228 static const struct spi_device_id lattice_ecp3_id[] = {
229 { "ecp3-17", 0 },
230 { "ecp3-35", 0 },
231 { }
232 };
233 MODULE_DEVICE_TABLE(spi, lattice_ecp3_id);
234
235 static struct spi_driver lattice_ecp3_driver = {
236 .driver = {
237 .name = "lattice-ecp3",
238 },
239 .probe = lattice_ecp3_probe,
240 .remove = lattice_ecp3_remove,
241 .id_table = lattice_ecp3_id,
242 };
243
244 module_spi_driver(lattice_ecp3_driver);
245
246 MODULE_AUTHOR("Stefan Roese <sr@denx.de>");
247 MODULE_DESCRIPTION("Lattice ECP3 FPGA configuration via SPI");
248 MODULE_LICENSE("GPL");
249 MODULE_FIRMWARE(FIRMWARE_NAME);
250