1 /*
2 * Intel MIC Platform Software Stack (MPSS)
3 *
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, version 2, as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * The full GNU General Public License is included in this distribution in
16 * the file called "COPYING".
17 *
18 * Intel MIC Host driver.
19 *
20 */
21 #ifndef _MIC_DEVICE_H_
22 #define _MIC_DEVICE_H_
23
24 #include <linux/cdev.h>
25 #include <linux/idr.h>
26 #include <linux/notifier.h>
27 #include <linux/irqreturn.h>
28 #include <linux/dmaengine.h>
29 #include <linux/miscdevice.h>
30 #include <linux/mic_bus.h>
31 #include "../bus/scif_bus.h"
32 #include "../bus/vop_bus.h"
33 #include "../bus/cosm_bus.h"
34 #include "mic_intr.h"
35
36 /**
37 * enum mic_stepping - MIC stepping ids.
38 */
39 enum mic_stepping {
40 MIC_A0_STEP = 0x0,
41 MIC_B0_STEP = 0x10,
42 MIC_B1_STEP = 0x11,
43 MIC_C0_STEP = 0x20,
44 };
45
46 extern struct cosm_hw_ops cosm_hw_ops;
47
48 /**
49 * struct mic_device - MIC device information for each card.
50 *
51 * @mmio: MMIO bar information.
52 * @aper: Aperture bar information.
53 * @family: The MIC family to which this device belongs.
54 * @ops: MIC HW specific operations.
55 * @id: The unique device id for this MIC device.
56 * @stepping: Stepping ID.
57 * @pdev: Underlying PCI device.
58 * @mic_mutex: Mutex for synchronizing access to mic_device.
59 * @intr_ops: HW specific interrupt operations.
60 * @smpt_ops: Hardware specific SMPT operations.
61 * @smpt: MIC SMPT information.
62 * @intr_info: H/W specific interrupt information.
63 * @irq_info: The OS specific irq information
64 * @dbg_dir: debugfs directory of this MIC device.
65 * @bootaddr: MIC boot address.
66 * @dp: virtio device page
67 * @dp_dma_addr: virtio device page DMA address.
68 * @dma_mbdev: MIC BUS DMA device.
69 * @dma_ch - Array of DMA channels
70 * @num_dma_ch - Number of DMA channels available
71 * @scdev: SCIF device on the SCIF virtual bus.
72 * @vpdev: Virtio over PCIe device on the VOP virtual bus.
73 * @cosm_dev: COSM device
74 */
75 struct mic_device {
76 struct mic_mw mmio;
77 struct mic_mw aper;
78 enum mic_hw_family family;
79 struct mic_hw_ops *ops;
80 int id;
81 enum mic_stepping stepping;
82 struct pci_dev *pdev;
83 struct mutex mic_mutex;
84 struct mic_hw_intr_ops *intr_ops;
85 struct mic_smpt_ops *smpt_ops;
86 struct mic_smpt_info *smpt;
87 struct mic_intr_info *intr_info;
88 struct mic_irq_info irq_info;
89 struct dentry *dbg_dir;
90 u32 bootaddr;
91 void *dp;
92 dma_addr_t dp_dma_addr;
93 struct mbus_device *dma_mbdev;
94 struct dma_chan *dma_ch[MIC_MAX_DMA_CHAN];
95 int num_dma_ch;
96 struct scif_hw_dev *scdev;
97 struct vop_device *vpdev;
98 struct cosm_device *cosm_dev;
99 };
100
101 /**
102 * struct mic_hw_ops - MIC HW specific operations.
103 * @aper_bar: Aperture bar resource number.
104 * @mmio_bar: MMIO bar resource number.
105 * @read_spad: Read from scratch pad register.
106 * @write_spad: Write to scratch pad register.
107 * @send_intr: Send an interrupt for a particular doorbell on the card.
108 * @ack_interrupt: Hardware specific operations to ack the h/w on
109 * receipt of an interrupt.
110 * @intr_workarounds: Hardware specific workarounds needed after
111 * handling an interrupt.
112 * @reset: Reset the remote processor.
113 * @reset_fw_ready: Reset firmware ready field.
114 * @is_fw_ready: Check if firmware is ready for OS download.
115 * @send_firmware_intr: Send an interrupt to the card firmware.
116 * @load_mic_fw: Load firmware segments required to boot the card
117 * into card memory. This includes the kernel, command line, ramdisk etc.
118 * @get_postcode: Get post code status from firmware.
119 * @dma_filter: DMA filter function to be used.
120 */
121 struct mic_hw_ops {
122 u8 aper_bar;
123 u8 mmio_bar;
124 u32 (*read_spad)(struct mic_device *mdev, unsigned int idx);
125 void (*write_spad)(struct mic_device *mdev, unsigned int idx, u32 val);
126 void (*send_intr)(struct mic_device *mdev, int doorbell);
127 u32 (*ack_interrupt)(struct mic_device *mdev);
128 void (*intr_workarounds)(struct mic_device *mdev);
129 void (*reset)(struct mic_device *mdev);
130 void (*reset_fw_ready)(struct mic_device *mdev);
131 bool (*is_fw_ready)(struct mic_device *mdev);
132 void (*send_firmware_intr)(struct mic_device *mdev);
133 int (*load_mic_fw)(struct mic_device *mdev, const char *buf);
134 u32 (*get_postcode)(struct mic_device *mdev);
135 bool (*dma_filter)(struct dma_chan *chan, void *param);
136 };
137
138 /**
139 * mic_mmio_read - read from an MMIO register.
140 * @mw: MMIO register base virtual address.
141 * @offset: register offset.
142 *
143 * RETURNS: register value.
144 */
mic_mmio_read(struct mic_mw * mw,u32 offset)145 static inline u32 mic_mmio_read(struct mic_mw *mw, u32 offset)
146 {
147 return ioread32(mw->va + offset);
148 }
149
150 /**
151 * mic_mmio_write - write to an MMIO register.
152 * @mw: MMIO register base virtual address.
153 * @val: the data value to put into the register
154 * @offset: register offset.
155 *
156 * RETURNS: none.
157 */
158 static inline void
mic_mmio_write(struct mic_mw * mw,u32 val,u32 offset)159 mic_mmio_write(struct mic_mw *mw, u32 val, u32 offset)
160 {
161 iowrite32(val, mw->va + offset);
162 }
163
164 void mic_bootparam_init(struct mic_device *mdev);
165 void mic_create_debug_dir(struct mic_device *dev);
166 void mic_delete_debug_dir(struct mic_device *dev);
167 void __init mic_init_debugfs(void);
168 void mic_exit_debugfs(void);
169 #endif
170