1 /*
2 * Atmel SDMMC controller driver.
3 *
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/io.h>
21 #include <linux/kernel.h>
22 #include <linux/mmc/host.h>
23 #include <linux/mmc/slot-gpio.h>
24 #include <linux/module.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/pm.h>
28 #include <linux/pm_runtime.h>
29
30 #include "sdhci-pltfm.h"
31
32 #define SDMMC_MC1R 0x204
33 #define SDMMC_MC1R_DDR BIT(3)
34 #define SDMMC_MC1R_FCD BIT(7)
35 #define SDMMC_CACR 0x230
36 #define SDMMC_CACR_CAPWREN BIT(0)
37 #define SDMMC_CACR_KEY (0x46 << 8)
38
39 #define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */
40
41 struct sdhci_at91_priv {
42 struct clk *hclock;
43 struct clk *gck;
44 struct clk *mainck;
45 };
46
sdhci_at91_set_force_card_detect(struct sdhci_host * host)47 static void sdhci_at91_set_force_card_detect(struct sdhci_host *host)
48 {
49 u8 mc1r;
50
51 mc1r = readb(host->ioaddr + SDMMC_MC1R);
52 mc1r |= SDMMC_MC1R_FCD;
53 writeb(mc1r, host->ioaddr + SDMMC_MC1R);
54 }
55
sdhci_at91_set_clock(struct sdhci_host * host,unsigned int clock)56 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
57 {
58 u16 clk;
59 unsigned long timeout;
60
61 host->mmc->actual_clock = 0;
62
63 /*
64 * There is no requirement to disable the internal clock before
65 * changing the SD clock configuration. Moreover, disabling the
66 * internal clock, changing the configuration and re-enabling the
67 * internal clock causes some bugs. It can prevent to get the internal
68 * clock stable flag ready and an unexpected switch to the base clock
69 * when using presets.
70 */
71 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
72 clk &= SDHCI_CLOCK_INT_EN;
73 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
74
75 if (clock == 0)
76 return;
77
78 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
79
80 clk |= SDHCI_CLOCK_INT_EN;
81 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
82
83 /* Wait max 20 ms */
84 timeout = 20;
85 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
86 & SDHCI_CLOCK_INT_STABLE)) {
87 if (timeout == 0) {
88 pr_err("%s: Internal clock never stabilised.\n",
89 mmc_hostname(host->mmc));
90 return;
91 }
92 timeout--;
93 mdelay(1);
94 }
95
96 clk |= SDHCI_CLOCK_CARD_EN;
97 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
98 }
99
100 /*
101 * In this specific implementation of the SDHCI controller, the power register
102 * needs to have a valid voltage set even when the power supply is managed by
103 * an external regulator.
104 */
sdhci_at91_set_power(struct sdhci_host * host,unsigned char mode,unsigned short vdd)105 static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode,
106 unsigned short vdd)
107 {
108 if (!IS_ERR(host->mmc->supply.vmmc)) {
109 struct mmc_host *mmc = host->mmc;
110
111 spin_unlock_irq(&host->lock);
112 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
113 spin_lock_irq(&host->lock);
114 }
115 sdhci_set_power_noreg(host, mode, vdd);
116 }
117
sdhci_at91_set_uhs_signaling(struct sdhci_host * host,unsigned int timing)118 void sdhci_at91_set_uhs_signaling(struct sdhci_host *host, unsigned int timing)
119 {
120 if (timing == MMC_TIMING_MMC_DDR52)
121 sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R);
122 sdhci_set_uhs_signaling(host, timing);
123 }
124
sdhci_at91_reset(struct sdhci_host * host,u8 mask)125 static void sdhci_at91_reset(struct sdhci_host *host, u8 mask)
126 {
127 sdhci_reset(host, mask);
128
129 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
130 sdhci_at91_set_force_card_detect(host);
131 }
132
133 static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
134 .set_clock = sdhci_at91_set_clock,
135 .set_bus_width = sdhci_set_bus_width,
136 .reset = sdhci_at91_reset,
137 .set_uhs_signaling = sdhci_at91_set_uhs_signaling,
138 .set_power = sdhci_at91_set_power,
139 };
140
141 static const struct sdhci_pltfm_data soc_data_sama5d2 = {
142 .ops = &sdhci_at91_sama5d2_ops,
143 };
144
145 static const struct of_device_id sdhci_at91_dt_match[] = {
146 { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 },
147 {}
148 };
149
150 #ifdef CONFIG_PM
sdhci_at91_runtime_suspend(struct device * dev)151 static int sdhci_at91_runtime_suspend(struct device *dev)
152 {
153 struct sdhci_host *host = dev_get_drvdata(dev);
154 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
155 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
156 int ret;
157
158 ret = sdhci_runtime_suspend_host(host);
159
160 clk_disable_unprepare(priv->gck);
161 clk_disable_unprepare(priv->hclock);
162 clk_disable_unprepare(priv->mainck);
163
164 return ret;
165 }
166
sdhci_at91_runtime_resume(struct device * dev)167 static int sdhci_at91_runtime_resume(struct device *dev)
168 {
169 struct sdhci_host *host = dev_get_drvdata(dev);
170 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
171 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
172 int ret;
173
174 ret = clk_prepare_enable(priv->mainck);
175 if (ret) {
176 dev_err(dev, "can't enable mainck\n");
177 return ret;
178 }
179
180 ret = clk_prepare_enable(priv->hclock);
181 if (ret) {
182 dev_err(dev, "can't enable hclock\n");
183 return ret;
184 }
185
186 ret = clk_prepare_enable(priv->gck);
187 if (ret) {
188 dev_err(dev, "can't enable gck\n");
189 return ret;
190 }
191
192 return sdhci_runtime_resume_host(host);
193 }
194 #endif /* CONFIG_PM */
195
196 static const struct dev_pm_ops sdhci_at91_dev_pm_ops = {
197 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
198 pm_runtime_force_resume)
199 SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend,
200 sdhci_at91_runtime_resume,
201 NULL)
202 };
203
sdhci_at91_probe(struct platform_device * pdev)204 static int sdhci_at91_probe(struct platform_device *pdev)
205 {
206 const struct of_device_id *match;
207 const struct sdhci_pltfm_data *soc_data;
208 struct sdhci_host *host;
209 struct sdhci_pltfm_host *pltfm_host;
210 struct sdhci_at91_priv *priv;
211 unsigned int caps0, caps1;
212 unsigned int clk_base, clk_mul;
213 unsigned int gck_rate, real_gck_rate;
214 int ret;
215 unsigned int preset_div;
216
217 match = of_match_device(sdhci_at91_dt_match, &pdev->dev);
218 if (!match)
219 return -EINVAL;
220 soc_data = match->data;
221
222 host = sdhci_pltfm_init(pdev, soc_data, sizeof(*priv));
223 if (IS_ERR(host))
224 return PTR_ERR(host);
225
226 pltfm_host = sdhci_priv(host);
227 priv = sdhci_pltfm_priv(pltfm_host);
228
229 priv->mainck = devm_clk_get(&pdev->dev, "baseclk");
230 if (IS_ERR(priv->mainck)) {
231 dev_err(&pdev->dev, "failed to get baseclk\n");
232 return PTR_ERR(priv->mainck);
233 }
234
235 priv->hclock = devm_clk_get(&pdev->dev, "hclock");
236 if (IS_ERR(priv->hclock)) {
237 dev_err(&pdev->dev, "failed to get hclock\n");
238 return PTR_ERR(priv->hclock);
239 }
240
241 priv->gck = devm_clk_get(&pdev->dev, "multclk");
242 if (IS_ERR(priv->gck)) {
243 dev_err(&pdev->dev, "failed to get multclk\n");
244 return PTR_ERR(priv->gck);
245 }
246
247 /*
248 * The mult clock is provided by as a generated clock by the PMC
249 * controller. In order to set the rate of gck, we have to get the
250 * base clock rate and the clock mult from capabilities.
251 */
252 clk_prepare_enable(priv->hclock);
253 caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES);
254 caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1);
255 clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
256 clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
257 gck_rate = clk_base * 1000000 * (clk_mul + 1);
258 ret = clk_set_rate(priv->gck, gck_rate);
259 if (ret < 0) {
260 dev_err(&pdev->dev, "failed to set gck");
261 goto hclock_disable_unprepare;
262 }
263 /*
264 * We need to check if we have the requested rate for gck because in
265 * some cases this rate could be not supported. If it happens, the rate
266 * is the closest one gck can provide. We have to update the value
267 * of clk mul.
268 */
269 real_gck_rate = clk_get_rate(priv->gck);
270 if (real_gck_rate != gck_rate) {
271 clk_mul = real_gck_rate / (clk_base * 1000000) - 1;
272 caps1 &= (~SDHCI_CLOCK_MUL_MASK);
273 caps1 |= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) & SDHCI_CLOCK_MUL_MASK);
274 /* Set capabilities in r/w mode. */
275 writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR);
276 writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1);
277 /* Set capabilities in ro mode. */
278 writel(0, host->ioaddr + SDMMC_CACR);
279 dev_info(&pdev->dev, "update clk mul to %u as gck rate is %u Hz\n",
280 clk_mul, real_gck_rate);
281 }
282
283 /*
284 * We have to set preset values because it depends on the clk_mul
285 * value. Moreover, SDR104 is supported in a degraded mode since the
286 * maximum sd clock value is 120 MHz instead of 208 MHz. For that
287 * reason, we need to use presets to support SDR104.
288 */
289 preset_div = DIV_ROUND_UP(real_gck_rate, 24000000) - 1;
290 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
291 host->ioaddr + SDHCI_PRESET_FOR_SDR12);
292 preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
293 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
294 host->ioaddr + SDHCI_PRESET_FOR_SDR25);
295 preset_div = DIV_ROUND_UP(real_gck_rate, 100000000) - 1;
296 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
297 host->ioaddr + SDHCI_PRESET_FOR_SDR50);
298 preset_div = DIV_ROUND_UP(real_gck_rate, 120000000) - 1;
299 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
300 host->ioaddr + SDHCI_PRESET_FOR_SDR104);
301 preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
302 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
303 host->ioaddr + SDHCI_PRESET_FOR_DDR50);
304
305 clk_prepare_enable(priv->mainck);
306 clk_prepare_enable(priv->gck);
307
308 ret = mmc_of_parse(host->mmc);
309 if (ret)
310 goto clocks_disable_unprepare;
311
312 sdhci_get_of_property(pdev);
313
314 pm_runtime_get_noresume(&pdev->dev);
315 pm_runtime_set_active(&pdev->dev);
316 pm_runtime_enable(&pdev->dev);
317 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
318 pm_runtime_use_autosuspend(&pdev->dev);
319
320 ret = sdhci_add_host(host);
321 if (ret)
322 goto pm_runtime_disable;
323
324 /*
325 * When calling sdhci_runtime_suspend_host(), the sdhci layer makes
326 * the assumption that all the clocks of the controller are disabled.
327 * It means we can't get irq from it when it is runtime suspended.
328 * For that reason, it is not planned to wake-up on a card detect irq
329 * from the controller.
330 * If we want to use runtime PM and to be able to wake-up on card
331 * insertion, we have to use a GPIO for the card detection or we can
332 * use polling. Be aware that using polling will resume/suspend the
333 * controller between each attempt.
334 * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries
335 * to enable polling via device tree with broken-cd property.
336 */
337 if (mmc_card_is_removable(host->mmc) &&
338 mmc_gpio_get_cd(host->mmc) < 0) {
339 host->mmc->caps |= MMC_CAP_NEEDS_POLL;
340 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
341 }
342
343 /*
344 * If the device attached to the MMC bus is not removable, it is safer
345 * to set the Force Card Detect bit. People often don't connect the
346 * card detect signal and use this pin for another purpose. If the card
347 * detect pin is not muxed to SDHCI controller, a default value is
348 * used. This value can be different from a SoC revision to another
349 * one. Problems come when this default value is not card present. To
350 * avoid this case, if the device is non removable then the card
351 * detection procedure using the SDMCC_CD signal is bypassed.
352 * This bit is reset when a software reset for all command is performed
353 * so we need to implement our own reset function to set back this bit.
354 */
355 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
356 sdhci_at91_set_force_card_detect(host);
357
358 pm_runtime_put_autosuspend(&pdev->dev);
359
360 return 0;
361
362 pm_runtime_disable:
363 pm_runtime_disable(&pdev->dev);
364 pm_runtime_set_suspended(&pdev->dev);
365 pm_runtime_put_noidle(&pdev->dev);
366 clocks_disable_unprepare:
367 clk_disable_unprepare(priv->gck);
368 clk_disable_unprepare(priv->mainck);
369 hclock_disable_unprepare:
370 clk_disable_unprepare(priv->hclock);
371 sdhci_pltfm_free(pdev);
372 return ret;
373 }
374
sdhci_at91_remove(struct platform_device * pdev)375 static int sdhci_at91_remove(struct platform_device *pdev)
376 {
377 struct sdhci_host *host = platform_get_drvdata(pdev);
378 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
379 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
380 struct clk *gck = priv->gck;
381 struct clk *hclock = priv->hclock;
382 struct clk *mainck = priv->mainck;
383
384 pm_runtime_get_sync(&pdev->dev);
385 pm_runtime_disable(&pdev->dev);
386 pm_runtime_put_noidle(&pdev->dev);
387
388 sdhci_pltfm_unregister(pdev);
389
390 clk_disable_unprepare(gck);
391 clk_disable_unprepare(hclock);
392 clk_disable_unprepare(mainck);
393
394 return 0;
395 }
396
397 static struct platform_driver sdhci_at91_driver = {
398 .driver = {
399 .name = "sdhci-at91",
400 .of_match_table = sdhci_at91_dt_match,
401 .pm = &sdhci_at91_dev_pm_ops,
402 },
403 .probe = sdhci_at91_probe,
404 .remove = sdhci_at91_remove,
405 };
406
407 module_platform_driver(sdhci_at91_driver);
408
409 MODULE_DESCRIPTION("SDHCI driver for at91");
410 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
411 MODULE_LICENSE("GPL v2");
412