1 /******************************************************************************* 2 Copyright (C) 2007-2009 STMicroelectronics Ltd 3 4 This program is free software; you can redistribute it and/or modify it 5 under the terms and conditions of the GNU General Public License, 6 version 2, as published by the Free Software Foundation. 7 8 This program is distributed in the hope it will be useful, but WITHOUT 9 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 more details. 12 13 You should have received a copy of the GNU General Public License along with 14 this program; if not, write to the Free Software Foundation, Inc., 15 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16 17 The full GNU General Public License is included in this distribution in 18 the file called "COPYING". 19 20 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 21 *******************************************************************************/ 22 #ifndef __DWMAC1000_H__ 23 #define __DWMAC1000_H__ 24 25 #include <linux/phy.h> 26 #include "common.h" 27 28 #define GMAC_CONTROL 0x00000000 /* Configuration */ 29 #define GMAC_FRAME_FILTER 0x00000004 /* Frame Filter */ 30 #define GMAC_HASH_HIGH 0x00000008 /* Multicast Hash Table High */ 31 #define GMAC_HASH_LOW 0x0000000c /* Multicast Hash Table Low */ 32 #define GMAC_MII_ADDR 0x00000010 /* MII Address */ 33 #define GMAC_MII_DATA 0x00000014 /* MII Data */ 34 #define GMAC_FLOW_CTRL 0x00000018 /* Flow Control */ 35 #define GMAC_VLAN_TAG 0x0000001c /* VLAN Tag */ 36 #define GMAC_VERSION 0x00000020 /* GMAC CORE Version */ 37 #define GMAC_DEBUG 0x00000024 /* GMAC debug register */ 38 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */ 39 40 #define GMAC_INT_STATUS 0x00000038 /* interrupt status register */ 41 #define GMAC_INT_STATUS_PMT BIT(3) 42 #define GMAC_INT_STATUS_MMCIS BIT(4) 43 #define GMAC_INT_STATUS_MMCRIS BIT(5) 44 #define GMAC_INT_STATUS_MMCTIS BIT(6) 45 #define GMAC_INT_STATUS_MMCCSUM BIT(7) 46 #define GMAC_INT_STATUS_TSTAMP BIT(9) 47 #define GMAC_INT_STATUS_LPIIS BIT(10) 48 49 /* interrupt mask register */ 50 #define GMAC_INT_MASK 0x0000003c 51 #define GMAC_INT_DISABLE_RGMII BIT(0) 52 #define GMAC_INT_DISABLE_PCSLINK BIT(1) 53 #define GMAC_INT_DISABLE_PCSAN BIT(2) 54 #define GMAC_INT_DISABLE_PMT BIT(3) 55 #define GMAC_INT_DISABLE_TIMESTAMP BIT(9) 56 #define GMAC_INT_DISABLE_PCS (GMAC_INT_DISABLE_RGMII | \ 57 GMAC_INT_DISABLE_PCSLINK | \ 58 GMAC_INT_DISABLE_PCSAN) 59 #define GMAC_INT_DEFAULT_MASK (GMAC_INT_DISABLE_TIMESTAMP | \ 60 GMAC_INT_DISABLE_PCS) 61 62 /* PMT Control and Status */ 63 #define GMAC_PMT 0x0000002c 64 enum power_event { 65 pointer_reset = 0x80000000, 66 global_unicast = 0x00000200, 67 wake_up_rx_frame = 0x00000040, 68 magic_frame = 0x00000020, 69 wake_up_frame_en = 0x00000004, 70 magic_pkt_en = 0x00000002, 71 power_down = 0x00000001, 72 }; 73 74 /* Energy Efficient Ethernet (EEE) 75 * 76 * LPI status, timer and control register offset 77 */ 78 #define LPI_CTRL_STATUS 0x0030 79 #define LPI_TIMER_CTRL 0x0034 80 81 /* LPI control and status defines */ 82 #define LPI_CTRL_STATUS_LPITXA 0x00080000 /* Enable LPI TX Automate */ 83 #define LPI_CTRL_STATUS_PLSEN 0x00040000 /* Enable PHY Link Status */ 84 #define LPI_CTRL_STATUS_PLS 0x00020000 /* PHY Link Status */ 85 #define LPI_CTRL_STATUS_LPIEN 0x00010000 /* LPI Enable */ 86 #define LPI_CTRL_STATUS_RLPIST 0x00000200 /* Receive LPI state */ 87 #define LPI_CTRL_STATUS_TLPIST 0x00000100 /* Transmit LPI state */ 88 #define LPI_CTRL_STATUS_RLPIEX 0x00000008 /* Receive LPI Exit */ 89 #define LPI_CTRL_STATUS_RLPIEN 0x00000004 /* Receive LPI Entry */ 90 #define LPI_CTRL_STATUS_TLPIEX 0x00000002 /* Transmit LPI Exit */ 91 #define LPI_CTRL_STATUS_TLPIEN 0x00000001 /* Transmit LPI Entry */ 92 93 /* GMAC HW ADDR regs */ 94 #define GMAC_ADDR_HIGH(reg) (((reg > 15) ? 0x00000800 : 0x00000040) + \ 95 (reg * 8)) 96 #define GMAC_ADDR_LOW(reg) (((reg > 15) ? 0x00000804 : 0x00000044) + \ 97 (reg * 8)) 98 #define GMAC_MAX_PERFECT_ADDRESSES 1 99 100 #define GMAC_PCS_BASE 0x000000c0 /* PCS register base */ 101 #define GMAC_RGSMIIIS 0x000000d8 /* RGMII/SMII status */ 102 103 /* SGMII/RGMII status register */ 104 #define GMAC_RGSMIIIS_LNKMODE BIT(0) 105 #define GMAC_RGSMIIIS_SPEED GENMASK(2, 1) 106 #define GMAC_RGSMIIIS_SPEED_SHIFT 1 107 #define GMAC_RGSMIIIS_LNKSTS BIT(3) 108 #define GMAC_RGSMIIIS_JABTO BIT(4) 109 #define GMAC_RGSMIIIS_FALSECARDET BIT(5) 110 #define GMAC_RGSMIIIS_SMIDRXS BIT(16) 111 /* LNKMOD */ 112 #define GMAC_RGSMIIIS_LNKMOD_MASK 0x1 113 /* LNKSPEED */ 114 #define GMAC_RGSMIIIS_SPEED_125 0x2 115 #define GMAC_RGSMIIIS_SPEED_25 0x1 116 #define GMAC_RGSMIIIS_SPEED_2_5 0x0 117 118 /* GMAC Configuration defines */ 119 #define GMAC_CONTROL_2K 0x08000000 /* IEEE 802.3as 2K packets */ 120 #define GMAC_CONTROL_TC 0x01000000 /* Transmit Conf. in RGMII/SGMII */ 121 #define GMAC_CONTROL_WD 0x00800000 /* Disable Watchdog on receive */ 122 #define GMAC_CONTROL_JD 0x00400000 /* Jabber disable */ 123 #define GMAC_CONTROL_BE 0x00200000 /* Frame Burst Enable */ 124 #define GMAC_CONTROL_JE 0x00100000 /* Jumbo frame */ 125 enum inter_frame_gap { 126 GMAC_CONTROL_IFG_88 = 0x00040000, 127 GMAC_CONTROL_IFG_80 = 0x00020000, 128 GMAC_CONTROL_IFG_40 = 0x000e0000, 129 }; 130 #define GMAC_CONTROL_DCRS 0x00010000 /* Disable carrier sense */ 131 #define GMAC_CONTROL_PS 0x00008000 /* Port Select 0:GMI 1:MII */ 132 #define GMAC_CONTROL_FES 0x00004000 /* Speed 0:10 1:100 */ 133 #define GMAC_CONTROL_DO 0x00002000 /* Disable Rx Own */ 134 #define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */ 135 #define GMAC_CONTROL_DM 0x00000800 /* Duplex Mode */ 136 #define GMAC_CONTROL_IPC 0x00000400 /* Checksum Offload */ 137 #define GMAC_CONTROL_DR 0x00000200 /* Disable Retry */ 138 #define GMAC_CONTROL_LUD 0x00000100 /* Link up/down */ 139 #define GMAC_CONTROL_ACS 0x00000080 /* Auto Pad/FCS Stripping */ 140 #define GMAC_CONTROL_DC 0x00000010 /* Deferral Check */ 141 #define GMAC_CONTROL_TE 0x00000008 /* Transmitter Enable */ 142 #define GMAC_CONTROL_RE 0x00000004 /* Receiver Enable */ 143 144 #define GMAC_CORE_INIT (GMAC_CONTROL_JD | GMAC_CONTROL_PS | GMAC_CONTROL_ACS | \ 145 GMAC_CONTROL_BE | GMAC_CONTROL_DCRS) 146 147 /* GMAC Frame Filter defines */ 148 #define GMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */ 149 #define GMAC_FRAME_FILTER_HUC 0x00000002 /* Hash Unicast */ 150 #define GMAC_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */ 151 #define GMAC_FRAME_FILTER_DAIF 0x00000008 /* DA Inverse Filtering */ 152 #define GMAC_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */ 153 #define GMAC_FRAME_FILTER_DBF 0x00000020 /* Disable Broadcast frames */ 154 #define GMAC_FRAME_FILTER_SAIF 0x00000100 /* Inverse Filtering */ 155 #define GMAC_FRAME_FILTER_SAF 0x00000200 /* Source Address Filter */ 156 #define GMAC_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */ 157 #define GMAC_FRAME_FILTER_RA 0x80000000 /* Receive all mode */ 158 /* GMII ADDR defines */ 159 #define GMAC_MII_ADDR_WRITE 0x00000002 /* MII Write */ 160 #define GMAC_MII_ADDR_BUSY 0x00000001 /* MII Busy */ 161 /* GMAC FLOW CTRL defines */ 162 #define GMAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */ 163 #define GMAC_FLOW_CTRL_PT_SHIFT 16 164 #define GMAC_FLOW_CTRL_UP 0x00000008 /* Unicast pause frame enable */ 165 #define GMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */ 166 #define GMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */ 167 #define GMAC_FLOW_CTRL_FCB_BPA 0x00000001 /* Flow Control Busy ... */ 168 169 /* DEBUG Register defines */ 170 /* MTL TxStatus FIFO */ 171 #define GMAC_DEBUG_TXSTSFSTS BIT(25) /* MTL TxStatus FIFO Full Status */ 172 #define GMAC_DEBUG_TXFSTS BIT(24) /* MTL Tx FIFO Not Empty Status */ 173 #define GMAC_DEBUG_TWCSTS BIT(22) /* MTL Tx FIFO Write Controller */ 174 /* MTL Tx FIFO Read Controller Status */ 175 #define GMAC_DEBUG_TRCSTS_MASK GENMASK(21, 20) 176 #define GMAC_DEBUG_TRCSTS_SHIFT 20 177 #define GMAC_DEBUG_TRCSTS_IDLE 0 178 #define GMAC_DEBUG_TRCSTS_READ 1 179 #define GMAC_DEBUG_TRCSTS_TXW 2 180 #define GMAC_DEBUG_TRCSTS_WRITE 3 181 #define GMAC_DEBUG_TXPAUSED BIT(19) /* MAC Transmitter in PAUSE */ 182 /* MAC Transmit Frame Controller Status */ 183 #define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17) 184 #define GMAC_DEBUG_TFCSTS_SHIFT 17 185 #define GMAC_DEBUG_TFCSTS_IDLE 0 186 #define GMAC_DEBUG_TFCSTS_WAIT 1 187 #define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2 188 #define GMAC_DEBUG_TFCSTS_XFER 3 189 /* MAC GMII or MII Transmit Protocol Engine Status */ 190 #define GMAC_DEBUG_TPESTS BIT(16) 191 #define GMAC_DEBUG_RXFSTS_MASK GENMASK(9, 8) /* MTL Rx FIFO Fill-level */ 192 #define GMAC_DEBUG_RXFSTS_SHIFT 8 193 #define GMAC_DEBUG_RXFSTS_EMPTY 0 194 #define GMAC_DEBUG_RXFSTS_BT 1 195 #define GMAC_DEBUG_RXFSTS_AT 2 196 #define GMAC_DEBUG_RXFSTS_FULL 3 197 #define GMAC_DEBUG_RRCSTS_MASK GENMASK(6, 5) /* MTL Rx FIFO Read Controller */ 198 #define GMAC_DEBUG_RRCSTS_SHIFT 5 199 #define GMAC_DEBUG_RRCSTS_IDLE 0 200 #define GMAC_DEBUG_RRCSTS_RDATA 1 201 #define GMAC_DEBUG_RRCSTS_RSTAT 2 202 #define GMAC_DEBUG_RRCSTS_FLUSH 3 203 #define GMAC_DEBUG_RWCSTS BIT(4) /* MTL Rx FIFO Write Controller Active */ 204 /* MAC Receive Frame Controller FIFO Status */ 205 #define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1) 206 #define GMAC_DEBUG_RFCFCSTS_SHIFT 1 207 /* MAC GMII or MII Receive Protocol Engine Status */ 208 #define GMAC_DEBUG_RPESTS BIT(0) 209 210 /*--- DMA BLOCK defines ---*/ 211 /* DMA Bus Mode register defines */ 212 #define DMA_BUS_MODE_DA 0x00000002 /* Arbitration scheme */ 213 #define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */ 214 #define DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */ 215 /* Programmable burst length (passed thorugh platform)*/ 216 #define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */ 217 #define DMA_BUS_MODE_PBL_SHIFT 8 218 #define DMA_BUS_MODE_ATDS 0x00000080 /* Alternate Descriptor Size */ 219 220 enum rx_tx_priority_ratio { 221 double_ratio = 0x00004000, /* 2:1 */ 222 triple_ratio = 0x00008000, /* 3:1 */ 223 quadruple_ratio = 0x0000c000, /* 4:1 */ 224 }; 225 226 #define DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */ 227 #define DMA_BUS_MODE_MB 0x04000000 /* Mixed burst */ 228 #define DMA_BUS_MODE_RPBL_MASK 0x003e0000 /* Rx-Programmable Burst Len */ 229 #define DMA_BUS_MODE_RPBL_SHIFT 17 230 #define DMA_BUS_MODE_USP 0x00800000 231 #define DMA_BUS_MODE_MAXPBL 0x01000000 232 #define DMA_BUS_MODE_AAL 0x02000000 233 234 /* DMA CRS Control and Status Register Mapping */ 235 #define DMA_HOST_TX_DESC 0x00001048 /* Current Host Tx descriptor */ 236 #define DMA_HOST_RX_DESC 0x0000104c /* Current Host Rx descriptor */ 237 /* DMA Bus Mode register defines */ 238 #define DMA_BUS_PR_RATIO_MASK 0x0000c000 /* Rx/Tx priority ratio */ 239 #define DMA_BUS_PR_RATIO_SHIFT 14 240 #define DMA_BUS_FB 0x00010000 /* Fixed Burst */ 241 242 /* DMA operation mode defines (start/stop tx/rx are placed in common header)*/ 243 /* Disable Drop TCP/IP csum error */ 244 #define DMA_CONTROL_DT 0x04000000 245 #define DMA_CONTROL_RSF 0x02000000 /* Receive Store and Forward */ 246 #define DMA_CONTROL_DFF 0x01000000 /* Disaable flushing */ 247 /* Threshold for Activating the FC */ 248 enum rfa { 249 act_full_minus_1 = 0x00800000, 250 act_full_minus_2 = 0x00800200, 251 act_full_minus_3 = 0x00800400, 252 act_full_minus_4 = 0x00800600, 253 }; 254 /* Threshold for Deactivating the FC */ 255 enum rfd { 256 deac_full_minus_1 = 0x00400000, 257 deac_full_minus_2 = 0x00400800, 258 deac_full_minus_3 = 0x00401000, 259 deac_full_minus_4 = 0x00401800, 260 }; 261 #define DMA_CONTROL_TSF 0x00200000 /* Transmit Store and Forward */ 262 263 enum ttc_control { 264 DMA_CONTROL_TTC_64 = 0x00000000, 265 DMA_CONTROL_TTC_128 = 0x00004000, 266 DMA_CONTROL_TTC_192 = 0x00008000, 267 DMA_CONTROL_TTC_256 = 0x0000c000, 268 DMA_CONTROL_TTC_40 = 0x00010000, 269 DMA_CONTROL_TTC_32 = 0x00014000, 270 DMA_CONTROL_TTC_24 = 0x00018000, 271 DMA_CONTROL_TTC_16 = 0x0001c000, 272 }; 273 #define DMA_CONTROL_TC_TX_MASK 0xfffe3fff 274 275 #define DMA_CONTROL_EFC 0x00000100 276 #define DMA_CONTROL_FEF 0x00000080 277 #define DMA_CONTROL_FUF 0x00000040 278 279 /* Receive flow control activation field 280 * RFA field in DMA control register, bits 23,10:9 281 */ 282 #define DMA_CONTROL_RFA_MASK 0x00800600 283 284 /* Receive flow control deactivation field 285 * RFD field in DMA control register, bits 22,12:11 286 */ 287 #define DMA_CONTROL_RFD_MASK 0x00401800 288 289 /* RFD and RFA fields are encoded as follows 290 * 291 * Bit Field 292 * 0,00 - Full minus 1KB (only valid when rxfifo >= 4KB and EFC enabled) 293 * 0,01 - Full minus 2KB (only valid when rxfifo >= 4KB and EFC enabled) 294 * 0,10 - Full minus 3KB (only valid when rxfifo >= 4KB and EFC enabled) 295 * 0,11 - Full minus 4KB (only valid when rxfifo > 4KB and EFC enabled) 296 * 1,00 - Full minus 5KB (only valid when rxfifo > 8KB and EFC enabled) 297 * 1,01 - Full minus 6KB (only valid when rxfifo > 8KB and EFC enabled) 298 * 1,10 - Full minus 7KB (only valid when rxfifo > 8KB and EFC enabled) 299 * 1,11 - Reserved 300 * 301 * RFD should always be > RFA for a given FIFO size. RFD == RFA may work, 302 * but packet throughput performance may not be as expected. 303 * 304 * Be sure that bit 3 in GMAC Register 6 is set for Unicast Pause frame 305 * detection (IEEE Specification Requirement, Annex 31B, 31B.1, Pause 306 * Description). 307 * 308 * Be sure that DZPA (bit 7 in Flow Control Register, GMAC Register 6), 309 * is set to 0. This allows pause frames with a quanta of 0 to be sent 310 * as an XOFF message to the link peer. 311 */ 312 313 #define RFA_FULL_MINUS_1K 0x00000000 314 #define RFA_FULL_MINUS_2K 0x00000200 315 #define RFA_FULL_MINUS_3K 0x00000400 316 #define RFA_FULL_MINUS_4K 0x00000600 317 #define RFA_FULL_MINUS_5K 0x00800000 318 #define RFA_FULL_MINUS_6K 0x00800200 319 #define RFA_FULL_MINUS_7K 0x00800400 320 321 #define RFD_FULL_MINUS_1K 0x00000000 322 #define RFD_FULL_MINUS_2K 0x00000800 323 #define RFD_FULL_MINUS_3K 0x00001000 324 #define RFD_FULL_MINUS_4K 0x00001800 325 #define RFD_FULL_MINUS_5K 0x00400000 326 #define RFD_FULL_MINUS_6K 0x00400800 327 #define RFD_FULL_MINUS_7K 0x00401000 328 329 enum rtc_control { 330 DMA_CONTROL_RTC_64 = 0x00000000, 331 DMA_CONTROL_RTC_32 = 0x00000008, 332 DMA_CONTROL_RTC_96 = 0x00000010, 333 DMA_CONTROL_RTC_128 = 0x00000018, 334 }; 335 #define DMA_CONTROL_TC_RX_MASK 0xffffffe7 336 337 #define DMA_CONTROL_OSF 0x00000004 /* Operate on second frame */ 338 339 /* MMC registers offset */ 340 #define GMAC_MMC_CTRL 0x100 341 #define GMAC_MMC_RX_INTR 0x104 342 #define GMAC_MMC_TX_INTR 0x108 343 #define GMAC_MMC_RX_CSUM_OFFLOAD 0x208 344 #define GMAC_EXTHASH_BASE 0x500 345 346 extern const struct stmmac_dma_ops dwmac1000_dma_ops; 347 #endif /* __DWMAC1000_H__ */ 348