1 /*
2 * PCIe host controller driver for Freescale i.MX6 SoCs
3 *
4 * Copyright (C) 2013 Kosagi
5 * http://www.kosagi.com
6 *
7 * Author: Sean Cross <xobs@kosagi.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/gpio.h>
17 #include <linux/kernel.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
20 #include <linux/module.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_device.h>
23 #include <linux/pci.h>
24 #include <linux/platform_device.h>
25 #include <linux/regmap.h>
26 #include <linux/resource.h>
27 #include <linux/signal.h>
28 #include <linux/types.h>
29 #include <linux/interrupt.h>
30
31 #include "pcie-designware.h"
32
33 #define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp)
34
35 enum imx6_pcie_variants {
36 IMX6Q,
37 IMX6SX,
38 IMX6QP,
39 };
40
41 struct imx6_pcie {
42 struct pcie_port pp; /* pp.dbi_base is DT 0th resource */
43 int reset_gpio;
44 bool gpio_active_high;
45 struct clk *pcie_bus;
46 struct clk *pcie_phy;
47 struct clk *pcie_inbound_axi;
48 struct clk *pcie;
49 struct regmap *iomuxc_gpr;
50 enum imx6_pcie_variants variant;
51 u32 tx_deemph_gen1;
52 u32 tx_deemph_gen2_3p5db;
53 u32 tx_deemph_gen2_6db;
54 u32 tx_swing_full;
55 u32 tx_swing_low;
56 int link_gen;
57 };
58
59 /* PCIe Root Complex registers (memory-mapped) */
60 #define PCIE_RC_LCR 0x7c
61 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1
62 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2
63 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
64
65 #define PCIE_RC_LCSR 0x80
66
67 /* PCIe Port Logic registers (memory-mapped) */
68 #define PL_OFFSET 0x700
69 #define PCIE_PL_PFLR (PL_OFFSET + 0x08)
70 #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
71 #define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
72 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
73 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
74 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
75 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4)
76
77 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
78 #define PCIE_PHY_CTRL_DATA_LOC 0
79 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
80 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
81 #define PCIE_PHY_CTRL_WR_LOC 18
82 #define PCIE_PHY_CTRL_RD_LOC 19
83
84 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
85 #define PCIE_PHY_STAT_ACK_LOC 16
86
87 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
88 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
89
90 /* PHY registers (not memory-mapped) */
91 #define PCIE_PHY_RX_ASIC_OUT 0x100D
92 #define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0)
93
94 #define PHY_RX_OVRD_IN_LO 0x1005
95 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
96 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
97
pcie_phy_poll_ack(struct imx6_pcie * imx6_pcie,int exp_val)98 static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
99 {
100 struct pcie_port *pp = &imx6_pcie->pp;
101 u32 val;
102 u32 max_iterations = 10;
103 u32 wait_counter = 0;
104
105 do {
106 val = dw_pcie_readl_rc(pp, PCIE_PHY_STAT);
107 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
108 wait_counter++;
109
110 if (val == exp_val)
111 return 0;
112
113 udelay(1);
114 } while (wait_counter < max_iterations);
115
116 return -ETIMEDOUT;
117 }
118
pcie_phy_wait_ack(struct imx6_pcie * imx6_pcie,int addr)119 static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
120 {
121 struct pcie_port *pp = &imx6_pcie->pp;
122 u32 val;
123 int ret;
124
125 val = addr << PCIE_PHY_CTRL_DATA_LOC;
126 dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, val);
127
128 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
129 dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, val);
130
131 ret = pcie_phy_poll_ack(imx6_pcie, 1);
132 if (ret)
133 return ret;
134
135 val = addr << PCIE_PHY_CTRL_DATA_LOC;
136 dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, val);
137
138 return pcie_phy_poll_ack(imx6_pcie, 0);
139 }
140
141 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
pcie_phy_read(struct imx6_pcie * imx6_pcie,int addr,int * data)142 static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
143 {
144 struct pcie_port *pp = &imx6_pcie->pp;
145 u32 val, phy_ctl;
146 int ret;
147
148 ret = pcie_phy_wait_ack(imx6_pcie, addr);
149 if (ret)
150 return ret;
151
152 /* assert Read signal */
153 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
154 dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, phy_ctl);
155
156 ret = pcie_phy_poll_ack(imx6_pcie, 1);
157 if (ret)
158 return ret;
159
160 val = dw_pcie_readl_rc(pp, PCIE_PHY_STAT);
161 *data = val & 0xffff;
162
163 /* deassert Read signal */
164 dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, 0x00);
165
166 return pcie_phy_poll_ack(imx6_pcie, 0);
167 }
168
pcie_phy_write(struct imx6_pcie * imx6_pcie,int addr,int data)169 static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
170 {
171 struct pcie_port *pp = &imx6_pcie->pp;
172 u32 var;
173 int ret;
174
175 /* write addr */
176 /* cap addr */
177 ret = pcie_phy_wait_ack(imx6_pcie, addr);
178 if (ret)
179 return ret;
180
181 var = data << PCIE_PHY_CTRL_DATA_LOC;
182 dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, var);
183
184 /* capture data */
185 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
186 dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, var);
187
188 ret = pcie_phy_poll_ack(imx6_pcie, 1);
189 if (ret)
190 return ret;
191
192 /* deassert cap data */
193 var = data << PCIE_PHY_CTRL_DATA_LOC;
194 dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, var);
195
196 /* wait for ack de-assertion */
197 ret = pcie_phy_poll_ack(imx6_pcie, 0);
198 if (ret)
199 return ret;
200
201 /* assert wr signal */
202 var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
203 dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, var);
204
205 /* wait for ack */
206 ret = pcie_phy_poll_ack(imx6_pcie, 1);
207 if (ret)
208 return ret;
209
210 /* deassert wr signal */
211 var = data << PCIE_PHY_CTRL_DATA_LOC;
212 dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, var);
213
214 /* wait for ack de-assertion */
215 ret = pcie_phy_poll_ack(imx6_pcie, 0);
216 if (ret)
217 return ret;
218
219 dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, 0x0);
220
221 return 0;
222 }
223
imx6_pcie_reset_phy(struct imx6_pcie * imx6_pcie)224 static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
225 {
226 u32 tmp;
227
228 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
229 tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
230 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
231 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
232
233 usleep_range(2000, 3000);
234
235 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
236 tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
237 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
238 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
239 }
240
241 /* Added for PCI abort handling */
imx6q_pcie_abort_handler(unsigned long addr,unsigned int fsr,struct pt_regs * regs)242 static int imx6q_pcie_abort_handler(unsigned long addr,
243 unsigned int fsr, struct pt_regs *regs)
244 {
245 return 0;
246 }
247
imx6_pcie_assert_core_reset(struct imx6_pcie * imx6_pcie)248 static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
249 {
250 struct pcie_port *pp = &imx6_pcie->pp;
251 u32 val, gpr1, gpr12;
252
253 switch (imx6_pcie->variant) {
254 case IMX6SX:
255 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
256 IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
257 IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
258 /* Force PCIe PHY reset */
259 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
260 IMX6SX_GPR5_PCIE_BTNRST_RESET,
261 IMX6SX_GPR5_PCIE_BTNRST_RESET);
262 break;
263 case IMX6QP:
264 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
265 IMX6Q_GPR1_PCIE_SW_RST,
266 IMX6Q_GPR1_PCIE_SW_RST);
267 break;
268 case IMX6Q:
269 /*
270 * If the bootloader already enabled the link we need some
271 * special handling to get the core back into a state where
272 * it is safe to touch it for configuration. As there is
273 * no dedicated reset signal wired up for MX6QDL, we need
274 * to manually force LTSSM into "detect" state before
275 * completely disabling LTSSM, which is a prerequisite for
276 * core configuration.
277 *
278 * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we
279 * have a strong indication that the bootloader activated
280 * the link.
281 */
282 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &gpr1);
283 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &gpr12);
284
285 if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) &&
286 (gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) {
287 val = dw_pcie_readl_rc(pp, PCIE_PL_PFLR);
288 val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
289 val |= PCIE_PL_PFLR_FORCE_LINK;
290 dw_pcie_writel_rc(pp, PCIE_PL_PFLR, val);
291
292 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
293 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
294 }
295
296 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
297 IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
298 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
299 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
300 break;
301 }
302 }
303
imx6_pcie_enable_ref_clk(struct imx6_pcie * imx6_pcie)304 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
305 {
306 struct pcie_port *pp = &imx6_pcie->pp;
307 struct device *dev = pp->dev;
308 int ret = 0;
309
310 switch (imx6_pcie->variant) {
311 case IMX6SX:
312 ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
313 if (ret) {
314 dev_err(dev, "unable to enable pcie_axi clock\n");
315 break;
316 }
317
318 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
319 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
320 break;
321 case IMX6QP: /* FALLTHROUGH */
322 case IMX6Q:
323 /* power up core phy and enable ref clock */
324 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
325 IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
326 /*
327 * the async reset input need ref clock to sync internally,
328 * when the ref clock comes after reset, internal synced
329 * reset time is too short, cannot meet the requirement.
330 * add one ~10us delay here.
331 */
332 udelay(10);
333 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
334 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
335 break;
336 }
337
338 return ret;
339 }
340
imx6_pcie_deassert_core_reset(struct imx6_pcie * imx6_pcie)341 static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
342 {
343 struct pcie_port *pp = &imx6_pcie->pp;
344 struct device *dev = pp->dev;
345 int ret;
346
347 ret = clk_prepare_enable(imx6_pcie->pcie_phy);
348 if (ret) {
349 dev_err(dev, "unable to enable pcie_phy clock\n");
350 return;
351 }
352
353 ret = clk_prepare_enable(imx6_pcie->pcie_bus);
354 if (ret) {
355 dev_err(dev, "unable to enable pcie_bus clock\n");
356 goto err_pcie_bus;
357 }
358
359 ret = clk_prepare_enable(imx6_pcie->pcie);
360 if (ret) {
361 dev_err(dev, "unable to enable pcie clock\n");
362 goto err_pcie;
363 }
364
365 ret = imx6_pcie_enable_ref_clk(imx6_pcie);
366 if (ret) {
367 dev_err(dev, "unable to enable pcie ref clock\n");
368 goto err_ref_clk;
369 }
370
371 /* allow the clocks to stabilize */
372 usleep_range(200, 500);
373
374 /* Some boards don't have PCIe reset GPIO. */
375 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
376 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
377 imx6_pcie->gpio_active_high);
378 msleep(100);
379 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
380 !imx6_pcie->gpio_active_high);
381 }
382
383 switch (imx6_pcie->variant) {
384 case IMX6SX:
385 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
386 IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
387 break;
388 case IMX6QP:
389 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
390 IMX6Q_GPR1_PCIE_SW_RST, 0);
391
392 usleep_range(200, 500);
393 break;
394 case IMX6Q: /* Nothing to do */
395 break;
396 }
397
398 return;
399
400 err_ref_clk:
401 clk_disable_unprepare(imx6_pcie->pcie);
402 err_pcie:
403 clk_disable_unprepare(imx6_pcie->pcie_bus);
404 err_pcie_bus:
405 clk_disable_unprepare(imx6_pcie->pcie_phy);
406 }
407
imx6_pcie_init_phy(struct imx6_pcie * imx6_pcie)408 static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
409 {
410 if (imx6_pcie->variant == IMX6SX)
411 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
412 IMX6SX_GPR12_PCIE_RX_EQ_MASK,
413 IMX6SX_GPR12_PCIE_RX_EQ_2);
414
415 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
416 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
417
418 /* configure constant input signal to the pcie ctrl and phy */
419 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
420 IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
421 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
422 IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
423
424 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
425 IMX6Q_GPR8_TX_DEEMPH_GEN1,
426 imx6_pcie->tx_deemph_gen1 << 0);
427 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
428 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
429 imx6_pcie->tx_deemph_gen2_3p5db << 6);
430 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
431 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
432 imx6_pcie->tx_deemph_gen2_6db << 12);
433 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
434 IMX6Q_GPR8_TX_SWING_FULL,
435 imx6_pcie->tx_swing_full << 18);
436 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
437 IMX6Q_GPR8_TX_SWING_LOW,
438 imx6_pcie->tx_swing_low << 25);
439 }
440
imx6_pcie_wait_for_link(struct imx6_pcie * imx6_pcie)441 static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie)
442 {
443 struct pcie_port *pp = &imx6_pcie->pp;
444 struct device *dev = pp->dev;
445
446 /* check if the link is up or not */
447 if (!dw_pcie_wait_for_link(pp))
448 return 0;
449
450 dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
451 dw_pcie_readl_rc(pp, PCIE_PHY_DEBUG_R0),
452 dw_pcie_readl_rc(pp, PCIE_PHY_DEBUG_R1));
453 return -ETIMEDOUT;
454 }
455
imx6_pcie_wait_for_speed_change(struct imx6_pcie * imx6_pcie)456 static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
457 {
458 struct pcie_port *pp = &imx6_pcie->pp;
459 struct device *dev = pp->dev;
460 u32 tmp;
461 unsigned int retries;
462
463 for (retries = 0; retries < 200; retries++) {
464 tmp = dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL);
465 /* Test if the speed change finished. */
466 if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
467 return 0;
468 usleep_range(100, 1000);
469 }
470
471 dev_err(dev, "Speed change timeout\n");
472 return -EINVAL;
473 }
474
imx6_pcie_msi_handler(int irq,void * arg)475 static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
476 {
477 struct imx6_pcie *imx6_pcie = arg;
478 struct pcie_port *pp = &imx6_pcie->pp;
479
480 return dw_handle_msi_irq(pp);
481 }
482
imx6_pcie_establish_link(struct imx6_pcie * imx6_pcie)483 static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
484 {
485 struct pcie_port *pp = &imx6_pcie->pp;
486 struct device *dev = pp->dev;
487 u32 tmp;
488 int ret;
489
490 /*
491 * Force Gen1 operation when starting the link. In case the link is
492 * started in Gen2 mode, there is a possibility the devices on the
493 * bus will not be detected at all. This happens with PCIe switches.
494 */
495 tmp = dw_pcie_readl_rc(pp, PCIE_RC_LCR);
496 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
497 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
498 dw_pcie_writel_rc(pp, PCIE_RC_LCR, tmp);
499
500 /* Start LTSSM. */
501 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
502 IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
503
504 ret = imx6_pcie_wait_for_link(imx6_pcie);
505 if (ret) {
506 dev_info(dev, "Link never came up\n");
507 goto err_reset_phy;
508 }
509
510 if (imx6_pcie->link_gen == 2) {
511 /* Allow Gen2 mode after the link is up. */
512 tmp = dw_pcie_readl_rc(pp, PCIE_RC_LCR);
513 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
514 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
515 dw_pcie_writel_rc(pp, PCIE_RC_LCR, tmp);
516 } else {
517 dev_info(dev, "Link: Gen2 disabled\n");
518 }
519
520 /*
521 * Start Directed Speed Change so the best possible speed both link
522 * partners support can be negotiated.
523 */
524 tmp = dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL);
525 tmp |= PORT_LOGIC_SPEED_CHANGE;
526 dw_pcie_writel_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
527
528 ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
529 if (ret) {
530 dev_err(dev, "Failed to bring link up!\n");
531 goto err_reset_phy;
532 }
533
534 /* Make sure link training is finished as well! */
535 ret = imx6_pcie_wait_for_link(imx6_pcie);
536 if (ret) {
537 dev_err(dev, "Failed to bring link up!\n");
538 goto err_reset_phy;
539 }
540
541 tmp = dw_pcie_readl_rc(pp, PCIE_RC_LCSR);
542 dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf);
543 return 0;
544
545 err_reset_phy:
546 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
547 dw_pcie_readl_rc(pp, PCIE_PHY_DEBUG_R0),
548 dw_pcie_readl_rc(pp, PCIE_PHY_DEBUG_R1));
549 imx6_pcie_reset_phy(imx6_pcie);
550 return ret;
551 }
552
imx6_pcie_host_init(struct pcie_port * pp)553 static void imx6_pcie_host_init(struct pcie_port *pp)
554 {
555 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
556
557 imx6_pcie_assert_core_reset(imx6_pcie);
558 imx6_pcie_init_phy(imx6_pcie);
559 imx6_pcie_deassert_core_reset(imx6_pcie);
560 dw_pcie_setup_rc(pp);
561 imx6_pcie_establish_link(imx6_pcie);
562
563 if (IS_ENABLED(CONFIG_PCI_MSI))
564 dw_pcie_msi_init(pp);
565 }
566
imx6_pcie_link_up(struct pcie_port * pp)567 static int imx6_pcie_link_up(struct pcie_port *pp)
568 {
569 return dw_pcie_readl_rc(pp, PCIE_PHY_DEBUG_R1) &
570 PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
571 }
572
573 static struct pcie_host_ops imx6_pcie_host_ops = {
574 .link_up = imx6_pcie_link_up,
575 .host_init = imx6_pcie_host_init,
576 };
577
imx6_add_pcie_port(struct imx6_pcie * imx6_pcie,struct platform_device * pdev)578 static int __init imx6_add_pcie_port(struct imx6_pcie *imx6_pcie,
579 struct platform_device *pdev)
580 {
581 struct pcie_port *pp = &imx6_pcie->pp;
582 struct device *dev = pp->dev;
583 int ret;
584
585 if (IS_ENABLED(CONFIG_PCI_MSI)) {
586 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
587 if (pp->msi_irq <= 0) {
588 dev_err(dev, "failed to get MSI irq\n");
589 return -ENODEV;
590 }
591
592 ret = devm_request_irq(dev, pp->msi_irq,
593 imx6_pcie_msi_handler,
594 IRQF_SHARED | IRQF_NO_THREAD,
595 "mx6-pcie-msi", imx6_pcie);
596 if (ret) {
597 dev_err(dev, "failed to request MSI irq\n");
598 return ret;
599 }
600 }
601
602 pp->root_bus_nr = -1;
603 pp->ops = &imx6_pcie_host_ops;
604
605 ret = dw_pcie_host_init(pp);
606 if (ret) {
607 dev_err(dev, "failed to initialize host\n");
608 return ret;
609 }
610
611 return 0;
612 }
613
imx6_pcie_probe(struct platform_device * pdev)614 static int __init imx6_pcie_probe(struct platform_device *pdev)
615 {
616 struct device *dev = &pdev->dev;
617 struct imx6_pcie *imx6_pcie;
618 struct pcie_port *pp;
619 struct resource *dbi_base;
620 struct device_node *node = dev->of_node;
621 int ret;
622
623 imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
624 if (!imx6_pcie)
625 return -ENOMEM;
626
627 pp = &imx6_pcie->pp;
628 pp->dev = dev;
629
630 imx6_pcie->variant =
631 (enum imx6_pcie_variants)of_device_get_match_data(dev);
632
633 /* Added for PCI abort handling */
634 hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
635 "imprecise external abort");
636
637 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
638 pp->dbi_base = devm_ioremap_resource(dev, dbi_base);
639 if (IS_ERR(pp->dbi_base))
640 return PTR_ERR(pp->dbi_base);
641
642 /* Fetch GPIOs */
643 imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
644 imx6_pcie->gpio_active_high = of_property_read_bool(node,
645 "reset-gpio-active-high");
646 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
647 ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
648 imx6_pcie->gpio_active_high ?
649 GPIOF_OUT_INIT_HIGH :
650 GPIOF_OUT_INIT_LOW,
651 "PCIe reset");
652 if (ret) {
653 dev_err(dev, "unable to get reset gpio\n");
654 return ret;
655 }
656 }
657
658 /* Fetch clocks */
659 imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
660 if (IS_ERR(imx6_pcie->pcie_phy)) {
661 dev_err(dev, "pcie_phy clock source missing or invalid\n");
662 return PTR_ERR(imx6_pcie->pcie_phy);
663 }
664
665 imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus");
666 if (IS_ERR(imx6_pcie->pcie_bus)) {
667 dev_err(dev, "pcie_bus clock source missing or invalid\n");
668 return PTR_ERR(imx6_pcie->pcie_bus);
669 }
670
671 imx6_pcie->pcie = devm_clk_get(dev, "pcie");
672 if (IS_ERR(imx6_pcie->pcie)) {
673 dev_err(dev, "pcie clock source missing or invalid\n");
674 return PTR_ERR(imx6_pcie->pcie);
675 }
676
677 if (imx6_pcie->variant == IMX6SX) {
678 imx6_pcie->pcie_inbound_axi = devm_clk_get(dev,
679 "pcie_inbound_axi");
680 if (IS_ERR(imx6_pcie->pcie_inbound_axi)) {
681 dev_err(dev,
682 "pcie_incbound_axi clock missing or invalid\n");
683 return PTR_ERR(imx6_pcie->pcie_inbound_axi);
684 }
685 }
686
687 /* Grab GPR config register range */
688 imx6_pcie->iomuxc_gpr =
689 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
690 if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
691 dev_err(dev, "unable to find iomuxc registers\n");
692 return PTR_ERR(imx6_pcie->iomuxc_gpr);
693 }
694
695 /* Grab PCIe PHY Tx Settings */
696 if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
697 &imx6_pcie->tx_deemph_gen1))
698 imx6_pcie->tx_deemph_gen1 = 0;
699
700 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
701 &imx6_pcie->tx_deemph_gen2_3p5db))
702 imx6_pcie->tx_deemph_gen2_3p5db = 0;
703
704 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
705 &imx6_pcie->tx_deemph_gen2_6db))
706 imx6_pcie->tx_deemph_gen2_6db = 20;
707
708 if (of_property_read_u32(node, "fsl,tx-swing-full",
709 &imx6_pcie->tx_swing_full))
710 imx6_pcie->tx_swing_full = 127;
711
712 if (of_property_read_u32(node, "fsl,tx-swing-low",
713 &imx6_pcie->tx_swing_low))
714 imx6_pcie->tx_swing_low = 127;
715
716 /* Limit link speed */
717 ret = of_property_read_u32(node, "fsl,max-link-speed",
718 &imx6_pcie->link_gen);
719 if (ret)
720 imx6_pcie->link_gen = 1;
721
722 ret = imx6_add_pcie_port(imx6_pcie, pdev);
723 if (ret < 0)
724 return ret;
725
726 platform_set_drvdata(pdev, imx6_pcie);
727 return 0;
728 }
729
imx6_pcie_shutdown(struct platform_device * pdev)730 static void imx6_pcie_shutdown(struct platform_device *pdev)
731 {
732 struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
733
734 /* bring down link, so bootloader gets clean state in case of reboot */
735 imx6_pcie_assert_core_reset(imx6_pcie);
736 }
737
738 static const struct of_device_id imx6_pcie_of_match[] = {
739 { .compatible = "fsl,imx6q-pcie", .data = (void *)IMX6Q, },
740 { .compatible = "fsl,imx6sx-pcie", .data = (void *)IMX6SX, },
741 { .compatible = "fsl,imx6qp-pcie", .data = (void *)IMX6QP, },
742 {},
743 };
744
745 static struct platform_driver imx6_pcie_driver = {
746 .driver = {
747 .name = "imx6q-pcie",
748 .of_match_table = imx6_pcie_of_match,
749 },
750 .shutdown = imx6_pcie_shutdown,
751 };
752
imx6_pcie_init(void)753 static int __init imx6_pcie_init(void)
754 {
755 return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
756 }
757 device_initcall(imx6_pcie_init);
758