1 /*
2 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
3 *
4 * Author: Ley Foon Tan <lftan@altera.com>
5 * Description: Altera PCIe host controller driver
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/irqchip/chained_irq.h>
23 #include <linux/init.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_pci.h>
27 #include <linux/pci.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
30
31 #define RP_TX_REG0 0x2000
32 #define RP_TX_REG1 0x2004
33 #define RP_TX_CNTRL 0x2008
34 #define RP_TX_EOP 0x2
35 #define RP_TX_SOP 0x1
36 #define RP_RXCPL_STATUS 0x2010
37 #define RP_RXCPL_EOP 0x2
38 #define RP_RXCPL_SOP 0x1
39 #define RP_RXCPL_REG0 0x2014
40 #define RP_RXCPL_REG1 0x2018
41 #define P2A_INT_STATUS 0x3060
42 #define P2A_INT_STS_ALL 0xf
43 #define P2A_INT_ENABLE 0x3070
44 #define P2A_INT_ENA_ALL 0xf
45 #define RP_LTSSM 0x3c64
46 #define RP_LTSSM_MASK 0x1f
47 #define LTSSM_L0 0xf
48
49 #define PCIE_CAP_OFFSET 0x80
50 /* TLP configuration type 0 and 1 */
51 #define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */
52 #define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */
53 #define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */
54 #define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */
55 #define TLP_PAYLOAD_SIZE 0x01
56 #define TLP_READ_TAG 0x1d
57 #define TLP_WRITE_TAG 0x10
58 #define RP_DEVFN 0
59 #define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
60 #define TLP_CFGRD_DW0(pcie, bus) \
61 ((((bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0 \
62 : TLP_FMTTYPE_CFGRD1) << 24) | \
63 TLP_PAYLOAD_SIZE)
64 #define TLP_CFGWR_DW0(pcie, bus) \
65 ((((bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGWR0 \
66 : TLP_FMTTYPE_CFGWR1) << 24) | \
67 TLP_PAYLOAD_SIZE)
68 #define TLP_CFG_DW1(pcie, tag, be) \
69 (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
70 #define TLP_CFG_DW2(bus, devfn, offset) \
71 (((bus) << 24) | ((devfn) << 16) | (offset))
72 #define TLP_COMP_STATUS(s) (((s) >> 12) & 7)
73 #define TLP_HDR_SIZE 3
74 #define TLP_LOOP 500
75
76 #define LINK_UP_TIMEOUT HZ
77 #define LINK_RETRAIN_TIMEOUT HZ
78
79 #define INTX_NUM 4
80
81 #define DWORD_MASK 3
82
83 struct altera_pcie {
84 struct platform_device *pdev;
85 void __iomem *cra_base; /* DT Cra */
86 int irq;
87 u8 root_bus_nr;
88 struct irq_domain *irq_domain;
89 struct resource bus_range;
90 struct list_head resources;
91 };
92
93 struct tlp_rp_regpair_t {
94 u32 ctrl;
95 u32 reg0;
96 u32 reg1;
97 };
98
cra_writel(struct altera_pcie * pcie,const u32 value,const u32 reg)99 static inline void cra_writel(struct altera_pcie *pcie, const u32 value,
100 const u32 reg)
101 {
102 writel_relaxed(value, pcie->cra_base + reg);
103 }
104
cra_readl(struct altera_pcie * pcie,const u32 reg)105 static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
106 {
107 return readl_relaxed(pcie->cra_base + reg);
108 }
109
altera_pcie_link_is_up(struct altera_pcie * pcie)110 static bool altera_pcie_link_is_up(struct altera_pcie *pcie)
111 {
112 return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
113 }
114
115 /*
116 * Altera PCIe port uses BAR0 of RC's configuration space as the translation
117 * from PCI bus to native BUS. Entire DDR region is mapped into PCIe space
118 * using these registers, so it can be reached by DMA from EP devices.
119 * This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt
120 * from EP devices, eventually trigger interrupt to GIC. The BAR0 of bridge
121 * should be hidden during enumeration to avoid the sizing and resource
122 * allocation by PCIe core.
123 */
altera_pcie_hide_rc_bar(struct pci_bus * bus,unsigned int devfn,int offset)124 static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn,
125 int offset)
126 {
127 if (pci_is_root_bus(bus) && (devfn == 0) &&
128 (offset == PCI_BASE_ADDRESS_0))
129 return true;
130
131 return false;
132 }
133
tlp_write_tx(struct altera_pcie * pcie,struct tlp_rp_regpair_t * tlp_rp_regdata)134 static void tlp_write_tx(struct altera_pcie *pcie,
135 struct tlp_rp_regpair_t *tlp_rp_regdata)
136 {
137 cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0);
138 cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1);
139 cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);
140 }
141
altera_pcie_valid_device(struct altera_pcie * pcie,struct pci_bus * bus,int dev)142 static bool altera_pcie_valid_device(struct altera_pcie *pcie,
143 struct pci_bus *bus, int dev)
144 {
145 /* If there is no link, then there is no device */
146 if (bus->number != pcie->root_bus_nr) {
147 if (!altera_pcie_link_is_up(pcie))
148 return false;
149 }
150
151 /* access only one slot on each root port */
152 if (bus->number == pcie->root_bus_nr && dev > 0)
153 return false;
154
155 return true;
156 }
157
tlp_read_packet(struct altera_pcie * pcie,u32 * value)158 static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
159 {
160 int i;
161 bool sop = 0;
162 u32 ctrl;
163 u32 reg0, reg1;
164 u32 comp_status = 1;
165
166 /*
167 * Minimum 2 loops to read TLP headers and 1 loop to read data
168 * payload.
169 */
170 for (i = 0; i < TLP_LOOP; i++) {
171 ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
172 if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) {
173 reg0 = cra_readl(pcie, RP_RXCPL_REG0);
174 reg1 = cra_readl(pcie, RP_RXCPL_REG1);
175
176 if (ctrl & RP_RXCPL_SOP) {
177 sop = true;
178 comp_status = TLP_COMP_STATUS(reg1);
179 }
180
181 if (ctrl & RP_RXCPL_EOP) {
182 if (comp_status)
183 return PCIBIOS_DEVICE_NOT_FOUND;
184
185 if (value)
186 *value = reg0;
187
188 return PCIBIOS_SUCCESSFUL;
189 }
190 }
191 udelay(5);
192 }
193
194 return PCIBIOS_DEVICE_NOT_FOUND;
195 }
196
tlp_write_packet(struct altera_pcie * pcie,u32 * headers,u32 data,bool align)197 static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
198 u32 data, bool align)
199 {
200 struct tlp_rp_regpair_t tlp_rp_regdata;
201
202 tlp_rp_regdata.reg0 = headers[0];
203 tlp_rp_regdata.reg1 = headers[1];
204 tlp_rp_regdata.ctrl = RP_TX_SOP;
205 tlp_write_tx(pcie, &tlp_rp_regdata);
206
207 if (align) {
208 tlp_rp_regdata.reg0 = headers[2];
209 tlp_rp_regdata.reg1 = 0;
210 tlp_rp_regdata.ctrl = 0;
211 tlp_write_tx(pcie, &tlp_rp_regdata);
212
213 tlp_rp_regdata.reg0 = data;
214 tlp_rp_regdata.reg1 = 0;
215 } else {
216 tlp_rp_regdata.reg0 = headers[2];
217 tlp_rp_regdata.reg1 = data;
218 }
219
220 tlp_rp_regdata.ctrl = RP_TX_EOP;
221 tlp_write_tx(pcie, &tlp_rp_regdata);
222 }
223
tlp_cfg_dword_read(struct altera_pcie * pcie,u8 bus,u32 devfn,int where,u8 byte_en,u32 * value)224 static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
225 int where, u8 byte_en, u32 *value)
226 {
227 u32 headers[TLP_HDR_SIZE];
228
229 headers[0] = TLP_CFGRD_DW0(pcie, bus);
230 headers[1] = TLP_CFG_DW1(pcie, TLP_READ_TAG, byte_en);
231 headers[2] = TLP_CFG_DW2(bus, devfn, where);
232
233 tlp_write_packet(pcie, headers, 0, false);
234
235 return tlp_read_packet(pcie, value);
236 }
237
tlp_cfg_dword_write(struct altera_pcie * pcie,u8 bus,u32 devfn,int where,u8 byte_en,u32 value)238 static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
239 int where, u8 byte_en, u32 value)
240 {
241 u32 headers[TLP_HDR_SIZE];
242 int ret;
243
244 headers[0] = TLP_CFGWR_DW0(pcie, bus);
245 headers[1] = TLP_CFG_DW1(pcie, TLP_WRITE_TAG, byte_en);
246 headers[2] = TLP_CFG_DW2(bus, devfn, where);
247
248 /* check alignment to Qword */
249 if ((where & 0x7) == 0)
250 tlp_write_packet(pcie, headers, value, true);
251 else
252 tlp_write_packet(pcie, headers, value, false);
253
254 ret = tlp_read_packet(pcie, NULL);
255 if (ret != PCIBIOS_SUCCESSFUL)
256 return ret;
257
258 /*
259 * Monitor changes to PCI_PRIMARY_BUS register on root port
260 * and update local copy of root bus number accordingly.
261 */
262 if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS))
263 pcie->root_bus_nr = (u8)(value);
264
265 return PCIBIOS_SUCCESSFUL;
266 }
267
_altera_pcie_cfg_read(struct altera_pcie * pcie,u8 busno,unsigned int devfn,int where,int size,u32 * value)268 static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno,
269 unsigned int devfn, int where, int size,
270 u32 *value)
271 {
272 int ret;
273 u32 data;
274 u8 byte_en;
275
276 switch (size) {
277 case 1:
278 byte_en = 1 << (where & 3);
279 break;
280 case 2:
281 byte_en = 3 << (where & 3);
282 break;
283 default:
284 byte_en = 0xf;
285 break;
286 }
287
288 ret = tlp_cfg_dword_read(pcie, busno, devfn,
289 (where & ~DWORD_MASK), byte_en, &data);
290 if (ret != PCIBIOS_SUCCESSFUL)
291 return ret;
292
293 switch (size) {
294 case 1:
295 *value = (data >> (8 * (where & 0x3))) & 0xff;
296 break;
297 case 2:
298 *value = (data >> (8 * (where & 0x2))) & 0xffff;
299 break;
300 default:
301 *value = data;
302 break;
303 }
304
305 return PCIBIOS_SUCCESSFUL;
306 }
307
_altera_pcie_cfg_write(struct altera_pcie * pcie,u8 busno,unsigned int devfn,int where,int size,u32 value)308 static int _altera_pcie_cfg_write(struct altera_pcie *pcie, u8 busno,
309 unsigned int devfn, int where, int size,
310 u32 value)
311 {
312 u32 data32;
313 u32 shift = 8 * (where & 3);
314 u8 byte_en;
315
316 switch (size) {
317 case 1:
318 data32 = (value & 0xff) << shift;
319 byte_en = 1 << (where & 3);
320 break;
321 case 2:
322 data32 = (value & 0xffff) << shift;
323 byte_en = 3 << (where & 3);
324 break;
325 default:
326 data32 = value;
327 byte_en = 0xf;
328 break;
329 }
330
331 return tlp_cfg_dword_write(pcie, busno, devfn, (where & ~DWORD_MASK),
332 byte_en, data32);
333 }
334
altera_pcie_cfg_read(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * value)335 static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
336 int where, int size, u32 *value)
337 {
338 struct altera_pcie *pcie = bus->sysdata;
339
340 if (altera_pcie_hide_rc_bar(bus, devfn, where))
341 return PCIBIOS_BAD_REGISTER_NUMBER;
342
343 if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn))) {
344 *value = 0xffffffff;
345 return PCIBIOS_DEVICE_NOT_FOUND;
346 }
347
348 return _altera_pcie_cfg_read(pcie, bus->number, devfn, where, size,
349 value);
350 }
351
altera_pcie_cfg_write(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 value)352 static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
353 int where, int size, u32 value)
354 {
355 struct altera_pcie *pcie = bus->sysdata;
356
357 if (altera_pcie_hide_rc_bar(bus, devfn, where))
358 return PCIBIOS_BAD_REGISTER_NUMBER;
359
360 if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn)))
361 return PCIBIOS_DEVICE_NOT_FOUND;
362
363 return _altera_pcie_cfg_write(pcie, bus->number, devfn, where, size,
364 value);
365 }
366
367 static struct pci_ops altera_pcie_ops = {
368 .read = altera_pcie_cfg_read,
369 .write = altera_pcie_cfg_write,
370 };
371
altera_read_cap_word(struct altera_pcie * pcie,u8 busno,unsigned int devfn,int offset,u16 * value)372 static int altera_read_cap_word(struct altera_pcie *pcie, u8 busno,
373 unsigned int devfn, int offset, u16 *value)
374 {
375 u32 data;
376 int ret;
377
378 ret = _altera_pcie_cfg_read(pcie, busno, devfn,
379 PCIE_CAP_OFFSET + offset, sizeof(*value),
380 &data);
381 *value = data;
382 return ret;
383 }
384
altera_write_cap_word(struct altera_pcie * pcie,u8 busno,unsigned int devfn,int offset,u16 value)385 static int altera_write_cap_word(struct altera_pcie *pcie, u8 busno,
386 unsigned int devfn, int offset, u16 value)
387 {
388 return _altera_pcie_cfg_write(pcie, busno, devfn,
389 PCIE_CAP_OFFSET + offset, sizeof(value),
390 value);
391 }
392
altera_wait_link_retrain(struct altera_pcie * pcie)393 static void altera_wait_link_retrain(struct altera_pcie *pcie)
394 {
395 struct device *dev = &pcie->pdev->dev;
396 u16 reg16;
397 unsigned long start_jiffies;
398
399 /* Wait for link training end. */
400 start_jiffies = jiffies;
401 for (;;) {
402 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
403 PCI_EXP_LNKSTA, ®16);
404 if (!(reg16 & PCI_EXP_LNKSTA_LT))
405 break;
406
407 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {
408 dev_err(dev, "link retrain timeout\n");
409 break;
410 }
411 udelay(100);
412 }
413
414 /* Wait for link is up */
415 start_jiffies = jiffies;
416 for (;;) {
417 if (altera_pcie_link_is_up(pcie))
418 break;
419
420 if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) {
421 dev_err(dev, "link up timeout\n");
422 break;
423 }
424 udelay(100);
425 }
426 }
427
altera_pcie_retrain(struct altera_pcie * pcie)428 static void altera_pcie_retrain(struct altera_pcie *pcie)
429 {
430 u16 linkcap, linkstat, linkctl;
431
432 if (!altera_pcie_link_is_up(pcie))
433 return;
434
435 /*
436 * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
437 * current speed is 2.5 GB/s.
438 */
439 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKCAP,
440 &linkcap);
441 if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
442 return;
443
444 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKSTA,
445 &linkstat);
446 if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
447 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
448 PCI_EXP_LNKCTL, &linkctl);
449 linkctl |= PCI_EXP_LNKCTL_RL;
450 altera_write_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
451 PCI_EXP_LNKCTL, linkctl);
452
453 altera_wait_link_retrain(pcie);
454 }
455 }
456
altera_pcie_intx_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)457 static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
458 irq_hw_number_t hwirq)
459 {
460 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
461 irq_set_chip_data(irq, domain->host_data);
462 return 0;
463 }
464
465 static const struct irq_domain_ops intx_domain_ops = {
466 .map = altera_pcie_intx_map,
467 };
468
altera_pcie_isr(struct irq_desc * desc)469 static void altera_pcie_isr(struct irq_desc *desc)
470 {
471 struct irq_chip *chip = irq_desc_get_chip(desc);
472 struct altera_pcie *pcie;
473 struct device *dev;
474 unsigned long status;
475 u32 bit;
476 u32 virq;
477
478 chained_irq_enter(chip, desc);
479 pcie = irq_desc_get_handler_data(desc);
480 dev = &pcie->pdev->dev;
481
482 while ((status = cra_readl(pcie, P2A_INT_STATUS)
483 & P2A_INT_STS_ALL) != 0) {
484 for_each_set_bit(bit, &status, INTX_NUM) {
485 /* clear interrupts */
486 cra_writel(pcie, 1 << bit, P2A_INT_STATUS);
487
488 virq = irq_find_mapping(pcie->irq_domain, bit + 1);
489 if (virq)
490 generic_handle_irq(virq);
491 else
492 dev_err(dev, "unexpected IRQ, INT%d\n", bit);
493 }
494 }
495
496 chained_irq_exit(chip, desc);
497 }
498
altera_pcie_parse_request_of_pci_ranges(struct altera_pcie * pcie)499 static int altera_pcie_parse_request_of_pci_ranges(struct altera_pcie *pcie)
500 {
501 int err, res_valid = 0;
502 struct device *dev = &pcie->pdev->dev;
503 struct device_node *np = dev->of_node;
504 struct resource_entry *win;
505
506 err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pcie->resources,
507 NULL);
508 if (err)
509 return err;
510
511 err = devm_request_pci_bus_resources(dev, &pcie->resources);
512 if (err)
513 goto out_release_res;
514
515 resource_list_for_each_entry(win, &pcie->resources) {
516 struct resource *res = win->res;
517
518 if (resource_type(res) == IORESOURCE_MEM)
519 res_valid |= !(res->flags & IORESOURCE_PREFETCH);
520 }
521
522 if (res_valid)
523 return 0;
524
525 dev_err(dev, "non-prefetchable memory resource required\n");
526 err = -EINVAL;
527
528 out_release_res:
529 pci_free_resource_list(&pcie->resources);
530 return err;
531 }
532
altera_pcie_init_irq_domain(struct altera_pcie * pcie)533 static int altera_pcie_init_irq_domain(struct altera_pcie *pcie)
534 {
535 struct device *dev = &pcie->pdev->dev;
536 struct device_node *node = dev->of_node;
537
538 /* Setup INTx */
539 pcie->irq_domain = irq_domain_add_linear(node, INTX_NUM + 1,
540 &intx_domain_ops, pcie);
541 if (!pcie->irq_domain) {
542 dev_err(dev, "Failed to get a INTx IRQ domain\n");
543 return -ENOMEM;
544 }
545
546 return 0;
547 }
548
altera_pcie_parse_dt(struct altera_pcie * pcie)549 static int altera_pcie_parse_dt(struct altera_pcie *pcie)
550 {
551 struct device *dev = &pcie->pdev->dev;
552 struct platform_device *pdev = pcie->pdev;
553 struct resource *cra;
554
555 cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra");
556 pcie->cra_base = devm_ioremap_resource(dev, cra);
557 if (IS_ERR(pcie->cra_base)) {
558 dev_err(dev, "failed to map cra memory\n");
559 return PTR_ERR(pcie->cra_base);
560 }
561
562 /* setup IRQ */
563 pcie->irq = platform_get_irq(pdev, 0);
564 if (pcie->irq <= 0) {
565 dev_err(dev, "failed to get IRQ: %d\n", pcie->irq);
566 return -EINVAL;
567 }
568
569 irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie);
570 return 0;
571 }
572
altera_pcie_host_init(struct altera_pcie * pcie)573 static void altera_pcie_host_init(struct altera_pcie *pcie)
574 {
575 altera_pcie_retrain(pcie);
576 }
577
altera_pcie_probe(struct platform_device * pdev)578 static int altera_pcie_probe(struct platform_device *pdev)
579 {
580 struct device *dev = &pdev->dev;
581 struct altera_pcie *pcie;
582 struct pci_bus *bus;
583 struct pci_bus *child;
584 int ret;
585
586 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
587 if (!pcie)
588 return -ENOMEM;
589
590 pcie->pdev = pdev;
591
592 ret = altera_pcie_parse_dt(pcie);
593 if (ret) {
594 dev_err(dev, "Parsing DT failed\n");
595 return ret;
596 }
597
598 INIT_LIST_HEAD(&pcie->resources);
599
600 ret = altera_pcie_parse_request_of_pci_ranges(pcie);
601 if (ret) {
602 dev_err(dev, "Failed add resources\n");
603 return ret;
604 }
605
606 ret = altera_pcie_init_irq_domain(pcie);
607 if (ret) {
608 dev_err(dev, "Failed creating IRQ Domain\n");
609 return ret;
610 }
611
612 /* clear all interrupts */
613 cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
614 /* enable all interrupts */
615 cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);
616 altera_pcie_host_init(pcie);
617
618 bus = pci_scan_root_bus(dev, pcie->root_bus_nr, &altera_pcie_ops,
619 pcie, &pcie->resources);
620 if (!bus)
621 return -ENOMEM;
622
623 pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
624 pci_assign_unassigned_bus_resources(bus);
625
626 /* Configure PCI Express setting. */
627 list_for_each_entry(child, &bus->children, node)
628 pcie_bus_configure_settings(child);
629
630 pci_bus_add_devices(bus);
631 return ret;
632 }
633
634 static const struct of_device_id altera_pcie_of_match[] = {
635 { .compatible = "altr,pcie-root-port-1.0", },
636 {},
637 };
638
639 static struct platform_driver altera_pcie_driver = {
640 .probe = altera_pcie_probe,
641 .driver = {
642 .name = "altera-pcie",
643 .of_match_table = altera_pcie_of_match,
644 .suppress_bind_attrs = true,
645 },
646 };
647
altera_pcie_init(void)648 static int altera_pcie_init(void)
649 {
650 return platform_driver_register(&altera_pcie_driver);
651 }
652 device_initcall(altera_pcie_init);
653