1 #ifndef WILC_WLAN_H 2 #define WILC_WLAN_H 3 4 #include <linux/types.h> 5 6 #define ISWILC1000(id) ((id & 0xfffff000) == 0x100000 ? 1 : 0) 7 8 /******************************************** 9 * 10 * Mac eth header length 11 * 12 ********************************************/ 13 #define DRIVER_HANDLER_SIZE 4 14 #define MAX_MAC_HDR_LEN 26 /* QOS_MAC_HDR_LEN */ 15 #define SUB_MSDU_HEADER_LENGTH 14 16 #define SNAP_HDR_LEN 8 17 #define ETHERNET_HDR_LEN 14 18 #define WORD_ALIGNMENT_PAD 0 19 20 #define ETH_ETHERNET_HDR_OFFSET (MAX_MAC_HDR_LEN + \ 21 SUB_MSDU_HEADER_LENGTH + \ 22 SNAP_HDR_LEN - \ 23 ETHERNET_HDR_LEN + \ 24 WORD_ALIGNMENT_PAD) 25 26 #define HOST_HDR_OFFSET 4 27 #define ETHERNET_HDR_LEN 14 28 #define IP_HDR_LEN 20 29 #define IP_HDR_OFFSET ETHERNET_HDR_LEN 30 #define UDP_HDR_OFFSET (IP_HDR_LEN + IP_HDR_OFFSET) 31 #define UDP_HDR_LEN 8 32 #define UDP_DATA_OFFSET (UDP_HDR_OFFSET + UDP_HDR_LEN) 33 #define ETH_CONFIG_PKT_HDR_LEN UDP_DATA_OFFSET 34 35 #define ETH_CONFIG_PKT_HDR_OFFSET (ETH_ETHERNET_HDR_OFFSET + \ 36 ETH_CONFIG_PKT_HDR_LEN) 37 38 /******************************************** 39 * 40 * Register Defines 41 * 42 ********************************************/ 43 #define WILC_PERIPH_REG_BASE 0x1000 44 #define WILC_CHANGING_VIR_IF 0x108c 45 #define WILC_CHIPID WILC_PERIPH_REG_BASE 46 #define WILC_GLB_RESET_0 (WILC_PERIPH_REG_BASE + 0x400) 47 #define WILC_PIN_MUX_0 (WILC_PERIPH_REG_BASE + 0x408) 48 #define WILC_HOST_TX_CTRL (WILC_PERIPH_REG_BASE + 0x6c) 49 #define WILC_HOST_RX_CTRL_0 (WILC_PERIPH_REG_BASE + 0x70) 50 #define WILC_HOST_RX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x74) 51 #define WILC_HOST_VMM_CTL (WILC_PERIPH_REG_BASE + 0x78) 52 #define WILC_HOST_RX_CTRL (WILC_PERIPH_REG_BASE + 0x80) 53 #define WILC_HOST_RX_EXTRA_SIZE (WILC_PERIPH_REG_BASE + 0x84) 54 #define WILC_HOST_TX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x88) 55 #define WILC_MISC (WILC_PERIPH_REG_BASE + 0x428) 56 #define WILC_INTR_REG_BASE (WILC_PERIPH_REG_BASE + 0xa00) 57 #define WILC_INTR_ENABLE WILC_INTR_REG_BASE 58 #define WILC_INTR2_ENABLE (WILC_INTR_REG_BASE + 4) 59 60 #define WILC_INTR_POLARITY (WILC_INTR_REG_BASE + 0x10) 61 #define WILC_INTR_TYPE (WILC_INTR_REG_BASE + 0x20) 62 #define WILC_INTR_CLEAR (WILC_INTR_REG_BASE + 0x30) 63 #define WILC_INTR_STATUS (WILC_INTR_REG_BASE + 0x40) 64 65 #define WILC_VMM_TBL_SIZE 64 66 #define WILC_VMM_TX_TBL_BASE 0x150400 67 #define WILC_VMM_RX_TBL_BASE 0x150500 68 69 #define WILC_VMM_BASE 0x150000 70 #define WILC_VMM_CORE_CTL WILC_VMM_BASE 71 #define WILC_VMM_TBL_CTL (WILC_VMM_BASE + 0x4) 72 #define WILC_VMM_TBL_ENTRY (WILC_VMM_BASE + 0x8) 73 #define WILC_VMM_TBL0_SIZE (WILC_VMM_BASE + 0xc) 74 #define WILC_VMM_TO_HOST_SIZE (WILC_VMM_BASE + 0x10) 75 #define WILC_VMM_CORE_CFG (WILC_VMM_BASE + 0x14) 76 #define WILC_VMM_TBL_ACTIVE (WILC_VMM_BASE + 040) 77 #define WILC_VMM_TBL_STATUS (WILC_VMM_BASE + 0x44) 78 79 #define WILC_SPI_REG_BASE 0xe800 80 #define WILC_SPI_CTL WILC_SPI_REG_BASE 81 #define WILC_SPI_MASTER_DMA_ADDR (WILC_SPI_REG_BASE + 0x4) 82 #define WILC_SPI_MASTER_DMA_COUNT (WILC_SPI_REG_BASE + 0x8) 83 #define WILC_SPI_SLAVE_DMA_ADDR (WILC_SPI_REG_BASE + 0xc) 84 #define WILC_SPI_SLAVE_DMA_COUNT (WILC_SPI_REG_BASE + 0x10) 85 #define WILC_SPI_TX_MODE (WILC_SPI_REG_BASE + 0x20) 86 #define WILC_SPI_PROTOCOL_CONFIG (WILC_SPI_REG_BASE + 0x24) 87 #define WILC_SPI_INTR_CTL (WILC_SPI_REG_BASE + 0x2c) 88 89 #define WILC_SPI_PROTOCOL_OFFSET (WILC_SPI_PROTOCOL_CONFIG - \ 90 WILC_SPI_REG_BASE) 91 92 #define WILC_AHB_DATA_MEM_BASE 0x30000 93 #define WILC_AHB_SHARE_MEM_BASE 0xd0000 94 95 #define WILC_VMM_TBL_RX_SHADOW_BASE WILC_AHB_SHARE_MEM_BASE 96 #define WILC_VMM_TBL_RX_SHADOW_SIZE 256 97 98 #define WILC_GP_REG_0 0x149c 99 #define WILC_GP_REG_1 0x14a0 100 101 #define WILC_HAVE_SDIO_IRQ_GPIO BIT(0) 102 #define WILC_HAVE_USE_PMU BIT(1) 103 #define WILC_HAVE_SLEEP_CLK_SRC_RTC BIT(2) 104 #define WILC_HAVE_SLEEP_CLK_SRC_XO BIT(3) 105 #define WILC_HAVE_EXT_PA_INV_TX_RX BIT(4) 106 #define WILC_HAVE_LEGACY_RF_SETTINGS BIT(5) 107 #define WILC_HAVE_XTAL_24 BIT(6) 108 #define WILC_HAVE_DISABLE_WILC_UART BIT(7) 109 #define WILC_HAVE_USE_IRQ_AS_HOST_WAKE BIT(8) 110 111 /******************************************** 112 * 113 * Wlan Defines 114 * 115 ********************************************/ 116 #define WILC_CFG_PKT 1 117 #define WILC_NET_PKT 0 118 #define WILC_MGMT_PKT 2 119 120 #define WILC_CFG_SET 1 121 #define WILC_CFG_QUERY 0 122 123 #define WILC_CFG_RSP 1 124 #define WILC_CFG_RSP_STATUS 2 125 #define WILC_CFG_RSP_SCAN 3 126 127 #define WILC_PLL_TO_SDIO 4 128 #define WILC_PLL_TO_SPI 2 129 #define ABORT_INT BIT(31) 130 131 #define LINUX_RX_SIZE (96 * 1024) 132 #define LINUX_TX_SIZE (64 * 1024) 133 134 #define MODALIAS "WILC_SPI" 135 #define GPIO_NUM 0x44 136 /*******************************************/ 137 /* E0 and later Interrupt flags. */ 138 /*******************************************/ 139 /*******************************************/ 140 /* E0 and later Interrupt flags. */ 141 /* IRQ Status word */ 142 /* 15:0 = DMA count in words. */ 143 /* 16: INT0 flag */ 144 /* 17: INT1 flag */ 145 /* 18: INT2 flag */ 146 /* 19: INT3 flag */ 147 /* 20: INT4 flag */ 148 /* 21: INT5 flag */ 149 /*******************************************/ 150 #define IRG_FLAGS_OFFSET 16 151 #define IRQ_DMA_WD_CNT_MASK ((1ul << IRG_FLAGS_OFFSET) - 1) 152 #define INT_0 BIT(IRG_FLAGS_OFFSET) 153 #define INT_1 BIT(IRG_FLAGS_OFFSET + 1) 154 #define INT_2 BIT(IRG_FLAGS_OFFSET + 2) 155 #define INT_3 BIT(IRG_FLAGS_OFFSET + 3) 156 #define INT_4 BIT(IRG_FLAGS_OFFSET + 4) 157 #define INT_5 BIT(IRG_FLAGS_OFFSET + 5) 158 #define MAX_NUM_INT 6 159 160 /*******************************************/ 161 /* E0 and later Interrupt flags. */ 162 /* IRQ Clear word */ 163 /* 0: Clear INT0 */ 164 /* 1: Clear INT1 */ 165 /* 2: Clear INT2 */ 166 /* 3: Clear INT3 */ 167 /* 4: Clear INT4 */ 168 /* 5: Clear INT5 */ 169 /* 6: Select VMM table 1 */ 170 /* 7: Select VMM table 2 */ 171 /* 8: Enable VMM */ 172 /*******************************************/ 173 #define CLR_INT0 BIT(0) 174 #define CLR_INT1 BIT(1) 175 #define CLR_INT2 BIT(2) 176 #define CLR_INT3 BIT(3) 177 #define CLR_INT4 BIT(4) 178 #define CLR_INT5 BIT(5) 179 #define SEL_VMM_TBL0 BIT(6) 180 #define SEL_VMM_TBL1 BIT(7) 181 #define EN_VMM BIT(8) 182 183 #define DATA_INT_EXT INT_0 184 #define PLL_INT_EXT INT_1 185 #define SLEEP_INT_EXT INT_2 186 #define ALL_INT_EXT (DATA_INT_EXT | PLL_INT_EXT | SLEEP_INT_EXT) 187 #define NUM_INT_EXT 3 188 189 #define DATA_INT_CLR CLR_INT0 190 #define PLL_INT_CLR CLR_INT1 191 #define SLEEP_INT_CLR CLR_INT2 192 193 #define ENABLE_RX_VMM (SEL_VMM_TBL1 | EN_VMM) 194 #define ENABLE_TX_VMM (SEL_VMM_TBL0 | EN_VMM) 195 /*time for expiring the completion of cfg packets*/ 196 #define CFG_PKTS_TIMEOUT 2000 197 /******************************************** 198 * 199 * Debug Type 200 * 201 ********************************************/ 202 typedef void (*wilc_debug_func)(u32, char *, ...); 203 204 /******************************************** 205 * 206 * Tx/Rx Queue Structure 207 * 208 ********************************************/ 209 210 struct txq_entry_t { 211 struct txq_entry_t *next; 212 struct txq_entry_t *prev; 213 int type; 214 int tcp_pending_ack_idx; 215 u8 *buffer; 216 int buffer_size; 217 void *priv; 218 int status; 219 void (*tx_complete_func)(void *, int); 220 }; 221 222 struct rxq_entry_t { 223 struct rxq_entry_t *next; 224 u8 *buffer; 225 int buffer_size; 226 }; 227 228 /******************************************** 229 * 230 * Host IF Structure 231 * 232 ********************************************/ 233 struct wilc; 234 struct wilc_hif_func { 235 int (*hif_init)(struct wilc *, bool resume); 236 int (*hif_deinit)(struct wilc *); 237 int (*hif_read_reg)(struct wilc *, u32, u32 *); 238 int (*hif_write_reg)(struct wilc *, u32, u32); 239 int (*hif_block_rx)(struct wilc *, u32, u8 *, u32); 240 int (*hif_block_tx)(struct wilc *, u32, u8 *, u32); 241 int (*hif_read_int)(struct wilc *, u32 *); 242 int (*hif_clear_int_ext)(struct wilc *, u32); 243 int (*hif_read_size)(struct wilc *, u32 *); 244 int (*hif_block_tx_ext)(struct wilc *, u32, u8 *, u32); 245 int (*hif_block_rx_ext)(struct wilc *, u32, u8 *, u32); 246 int (*hif_sync_ext)(struct wilc *, int); 247 int (*enable_interrupt)(struct wilc *nic); 248 void (*disable_interrupt)(struct wilc *nic); 249 }; 250 251 extern const struct wilc_hif_func wilc_hif_spi; 252 extern const struct wilc_hif_func wilc_hif_sdio; 253 254 /******************************************** 255 * 256 * Configuration Structure 257 * 258 ********************************************/ 259 260 #define MAX_CFG_FRAME_SIZE 1468 261 262 struct wilc_cfg_frame { 263 u8 ether_header[14]; 264 u8 ip_header[20]; 265 u8 udp_header[8]; 266 u8 wid_header[8]; 267 u8 frame[MAX_CFG_FRAME_SIZE]; 268 }; 269 270 struct wilc_cfg_rsp { 271 int type; 272 u32 seq_no; 273 }; 274 275 struct wilc; 276 struct wilc_vif; 277 278 int wilc_wlan_firmware_download(struct wilc *wilc, const u8 *buffer, 279 u32 buffer_size); 280 int wilc_wlan_start(struct wilc *); 281 int wilc_wlan_stop(struct wilc *); 282 int wilc_wlan_txq_add_net_pkt(struct net_device *dev, void *priv, u8 *buffer, 283 u32 buffer_size, wilc_tx_complete_func_t func); 284 int wilc_wlan_handle_txq(struct net_device *dev, u32 *txq_count); 285 void wilc_handle_isr(struct wilc *wilc); 286 void wilc_wlan_cleanup(struct net_device *dev); 287 int wilc_wlan_cfg_set(struct wilc_vif *vif, int start, u16 wid, u8 *buffer, 288 u32 buffer_size, int commit, u32 drv_handler); 289 int wilc_wlan_cfg_get(struct wilc_vif *vif, int start, u16 wid, int commit, 290 u32 drv_handler); 291 int wilc_wlan_cfg_get_val(u16 wid, u8 *buffer, u32 buffer_size); 292 int wilc_wlan_txq_add_mgmt_pkt(struct net_device *dev, void *priv, u8 *buffer, 293 u32 buffer_size, wilc_tx_complete_func_t func); 294 void wilc_chip_sleep_manually(struct wilc *wilc); 295 296 void wilc_enable_tcp_ack_filter(bool value); 297 int wilc_wlan_get_num_conn_ifcs(struct wilc *); 298 int wilc_mac_xmit(struct sk_buff *skb, struct net_device *dev); 299 300 int wilc_mac_open(struct net_device *ndev); 301 int wilc_mac_close(struct net_device *ndev); 302 303 void WILC_WFI_p2p_rx(struct net_device *dev, u8 *buff, u32 size); 304 void host_wakeup_notify(struct wilc *wilc); 305 void host_sleep_notify(struct wilc *wilc); 306 extern bool wilc_enable_ps; 307 void chip_allow_sleep(struct wilc *wilc); 308 void chip_wakeup(struct wilc *wilc); 309 int wilc_send_config_pkt(struct wilc_vif *vif, u8 mode, struct wid *wids, 310 u32 count, u32 drv); 311 #endif 312