1 /*
2 * RocketPort device driver for Linux
3 *
4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
5 *
6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 /*
24 * Kernel Synchronization:
25 *
26 * This driver has 2 kernel control paths - exception handlers (calls into the driver
27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
28 * are not used.
29 *
30 * Critical data:
31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
32 * serial port state information and the xmit_buf circular buffer. Protected by
33 * a per port spinlock.
34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
35 * is data to be transmitted. Protected by atomic bit operations.
36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
37 *
38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
39 * simultaneous access to the same port by more than one process.
40 */
41
42 /****** Defines ******/
43 #define ROCKET_PARANOIA_CHECK
44 #define ROCKET_DISABLE_SIMUSAGE
45
46 #undef ROCKET_SOFT_FLOW
47 #undef ROCKET_DEBUG_OPEN
48 #undef ROCKET_DEBUG_INTR
49 #undef ROCKET_DEBUG_WRITE
50 #undef ROCKET_DEBUG_FLOW
51 #undef ROCKET_DEBUG_THROTTLE
52 #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
53 #undef ROCKET_DEBUG_RECEIVE
54 #undef ROCKET_DEBUG_HANGUP
55 #undef REV_PCI_ORDER
56 #undef ROCKET_DEBUG_IO
57
58 #define POLL_PERIOD (HZ/100) /* Polling period .01 seconds (10ms) */
59
60 /****** Kernel includes ******/
61
62 #include <linux/module.h>
63 #include <linux/errno.h>
64 #include <linux/major.h>
65 #include <linux/kernel.h>
66 #include <linux/signal.h>
67 #include <linux/slab.h>
68 #include <linux/mm.h>
69 #include <linux/sched.h>
70 #include <linux/timer.h>
71 #include <linux/interrupt.h>
72 #include <linux/tty.h>
73 #include <linux/tty_driver.h>
74 #include <linux/tty_flip.h>
75 #include <linux/serial.h>
76 #include <linux/string.h>
77 #include <linux/fcntl.h>
78 #include <linux/ptrace.h>
79 #include <linux/mutex.h>
80 #include <linux/ioport.h>
81 #include <linux/delay.h>
82 #include <linux/completion.h>
83 #include <linux/wait.h>
84 #include <linux/pci.h>
85 #include <linux/uaccess.h>
86 #include <linux/atomic.h>
87 #include <asm/unaligned.h>
88 #include <linux/bitops.h>
89 #include <linux/spinlock.h>
90 #include <linux/init.h>
91
92 /****** RocketPort includes ******/
93
94 #include "rocket_int.h"
95 #include "rocket.h"
96
97 #define ROCKET_VERSION "2.09"
98 #define ROCKET_DATE "12-June-2003"
99
100 /****** RocketPort Local Variables ******/
101
102 static void rp_do_poll(unsigned long dummy);
103
104 static struct tty_driver *rocket_driver;
105
106 static struct rocket_version driver_version = {
107 ROCKET_VERSION, ROCKET_DATE
108 };
109
110 static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
111 static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
112 /* eg. Bit 0 indicates port 0 has xmit data, ... */
113 static atomic_t rp_num_ports_open; /* Number of serial ports open */
114 static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
115
116 static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
117 static unsigned long board2;
118 static unsigned long board3;
119 static unsigned long board4;
120 static unsigned long controller;
121 static bool support_low_speed;
122 static unsigned long modem1;
123 static unsigned long modem2;
124 static unsigned long modem3;
125 static unsigned long modem4;
126 static unsigned long pc104_1[8];
127 static unsigned long pc104_2[8];
128 static unsigned long pc104_3[8];
129 static unsigned long pc104_4[8];
130 static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
131
132 static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
133 static unsigned long rcktpt_io_addr[NUM_BOARDS];
134 static int rcktpt_type[NUM_BOARDS];
135 static int is_PCI[NUM_BOARDS];
136 static rocketModel_t rocketModel[NUM_BOARDS];
137 static int max_board;
138 static const struct tty_port_operations rocket_port_ops;
139
140 /*
141 * The following arrays define the interrupt bits corresponding to each AIOP.
142 * These bits are different between the ISA and regular PCI boards and the
143 * Universal PCI boards.
144 */
145
146 static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
147 AIOP_INTR_BIT_0,
148 AIOP_INTR_BIT_1,
149 AIOP_INTR_BIT_2,
150 AIOP_INTR_BIT_3
151 };
152
153 #ifdef CONFIG_PCI
154 static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
155 UPCI_AIOP_INTR_BIT_0,
156 UPCI_AIOP_INTR_BIT_1,
157 UPCI_AIOP_INTR_BIT_2,
158 UPCI_AIOP_INTR_BIT_3
159 };
160 #endif
161
162 static Byte_t RData[RDATASIZE] = {
163 0x00, 0x09, 0xf6, 0x82,
164 0x02, 0x09, 0x86, 0xfb,
165 0x04, 0x09, 0x00, 0x0a,
166 0x06, 0x09, 0x01, 0x0a,
167 0x08, 0x09, 0x8a, 0x13,
168 0x0a, 0x09, 0xc5, 0x11,
169 0x0c, 0x09, 0x86, 0x85,
170 0x0e, 0x09, 0x20, 0x0a,
171 0x10, 0x09, 0x21, 0x0a,
172 0x12, 0x09, 0x41, 0xff,
173 0x14, 0x09, 0x82, 0x00,
174 0x16, 0x09, 0x82, 0x7b,
175 0x18, 0x09, 0x8a, 0x7d,
176 0x1a, 0x09, 0x88, 0x81,
177 0x1c, 0x09, 0x86, 0x7a,
178 0x1e, 0x09, 0x84, 0x81,
179 0x20, 0x09, 0x82, 0x7c,
180 0x22, 0x09, 0x0a, 0x0a
181 };
182
183 static Byte_t RRegData[RREGDATASIZE] = {
184 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
185 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
186 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
187 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
188 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
189 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
190 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
191 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
192 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
193 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
194 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
195 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
196 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
197 };
198
199 static CONTROLLER_T sController[CTL_SIZE] = {
200 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
201 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
202 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
204 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
205 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
206 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
207 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
208 };
209
210 static Byte_t sBitMapClrTbl[8] = {
211 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
212 };
213
214 static Byte_t sBitMapSetTbl[8] = {
215 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
216 };
217
218 static int sClockPrescale = 0x14;
219
220 /*
221 * Line number is the ttySIx number (x), the Minor number. We
222 * assign them sequentially, starting at zero. The following
223 * array keeps track of the line number assigned to a given board/aiop/channel.
224 */
225 static unsigned char lineNumbers[MAX_RP_PORTS];
226 static unsigned long nextLineNumber;
227
228 /***** RocketPort Static Prototypes *********/
229 static int __init init_ISA(int i);
230 static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
231 static void rp_flush_buffer(struct tty_struct *tty);
232 static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
233 static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
234 static void rp_start(struct tty_struct *tty);
235 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
236 int ChanNum);
237 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
238 static void sFlushRxFIFO(CHANNEL_T * ChP);
239 static void sFlushTxFIFO(CHANNEL_T * ChP);
240 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
241 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
242 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
243 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
244 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
245 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
246 ByteIO_t * AiopIOList, int AiopIOListSize,
247 int IRQNum, Byte_t Frequency, int PeriodicOnly);
248 static int sReadAiopID(ByteIO_t io);
249 static int sReadAiopNumChan(WordIO_t io);
250
251 MODULE_AUTHOR("Theodore Ts'o");
252 MODULE_DESCRIPTION("Comtrol RocketPort driver");
253 module_param(board1, ulong, 0);
254 MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
255 module_param(board2, ulong, 0);
256 MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
257 module_param(board3, ulong, 0);
258 MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
259 module_param(board4, ulong, 0);
260 MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
261 module_param(controller, ulong, 0);
262 MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
263 module_param(support_low_speed, bool, 0);
264 MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
265 module_param(modem1, ulong, 0);
266 MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
267 module_param(modem2, ulong, 0);
268 MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
269 module_param(modem3, ulong, 0);
270 MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
271 module_param(modem4, ulong, 0);
272 MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
273 module_param_array(pc104_1, ulong, NULL, 0);
274 MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
275 module_param_array(pc104_2, ulong, NULL, 0);
276 MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
277 module_param_array(pc104_3, ulong, NULL, 0);
278 MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
279 module_param_array(pc104_4, ulong, NULL, 0);
280 MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
281
282 static int rp_init(void);
283 static void rp_cleanup_module(void);
284
285 module_init(rp_init);
286 module_exit(rp_cleanup_module);
287
288
289 MODULE_LICENSE("Dual BSD/GPL");
290
291 /*************************************************************************/
292 /* Module code starts here */
293
rocket_paranoia_check(struct r_port * info,const char * routine)294 static inline int rocket_paranoia_check(struct r_port *info,
295 const char *routine)
296 {
297 #ifdef ROCKET_PARANOIA_CHECK
298 if (!info)
299 return 1;
300 if (info->magic != RPORT_MAGIC) {
301 printk(KERN_WARNING "Warning: bad magic number for rocketport "
302 "struct in %s\n", routine);
303 return 1;
304 }
305 #endif
306 return 0;
307 }
308
309
310 /* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
311 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
312 * tty layer.
313 */
rp_do_receive(struct r_port * info,CHANNEL_t * cp,unsigned int ChanStatus)314 static void rp_do_receive(struct r_port *info, CHANNEL_t *cp,
315 unsigned int ChanStatus)
316 {
317 unsigned int CharNStat;
318 int ToRecv, wRecv, space;
319 unsigned char *cbuf;
320
321 ToRecv = sGetRxCnt(cp);
322 #ifdef ROCKET_DEBUG_INTR
323 printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
324 #endif
325 if (ToRecv == 0)
326 return;
327
328 /*
329 * if status indicates there are errored characters in the
330 * FIFO, then enter status mode (a word in FIFO holds
331 * character and status).
332 */
333 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
334 if (!(ChanStatus & STATMODE)) {
335 #ifdef ROCKET_DEBUG_RECEIVE
336 printk(KERN_INFO "Entering STATMODE...\n");
337 #endif
338 ChanStatus |= STATMODE;
339 sEnRxStatusMode(cp);
340 }
341 }
342
343 /*
344 * if we previously entered status mode, then read down the
345 * FIFO one word at a time, pulling apart the character and
346 * the status. Update error counters depending on status
347 */
348 if (ChanStatus & STATMODE) {
349 #ifdef ROCKET_DEBUG_RECEIVE
350 printk(KERN_INFO "Ignore %x, read %x...\n",
351 info->ignore_status_mask, info->read_status_mask);
352 #endif
353 while (ToRecv) {
354 char flag;
355
356 CharNStat = sInW(sGetTxRxDataIO(cp));
357 #ifdef ROCKET_DEBUG_RECEIVE
358 printk(KERN_INFO "%x...\n", CharNStat);
359 #endif
360 if (CharNStat & STMBREAKH)
361 CharNStat &= ~(STMFRAMEH | STMPARITYH);
362 if (CharNStat & info->ignore_status_mask) {
363 ToRecv--;
364 continue;
365 }
366 CharNStat &= info->read_status_mask;
367 if (CharNStat & STMBREAKH)
368 flag = TTY_BREAK;
369 else if (CharNStat & STMPARITYH)
370 flag = TTY_PARITY;
371 else if (CharNStat & STMFRAMEH)
372 flag = TTY_FRAME;
373 else if (CharNStat & STMRCVROVRH)
374 flag = TTY_OVERRUN;
375 else
376 flag = TTY_NORMAL;
377 tty_insert_flip_char(&info->port, CharNStat & 0xff,
378 flag);
379 ToRecv--;
380 }
381
382 /*
383 * after we've emptied the FIFO in status mode, turn
384 * status mode back off
385 */
386 if (sGetRxCnt(cp) == 0) {
387 #ifdef ROCKET_DEBUG_RECEIVE
388 printk(KERN_INFO "Status mode off.\n");
389 #endif
390 sDisRxStatusMode(cp);
391 }
392 } else {
393 /*
394 * we aren't in status mode, so read down the FIFO two
395 * characters at time by doing repeated word IO
396 * transfer.
397 */
398 space = tty_prepare_flip_string(&info->port, &cbuf, ToRecv);
399 if (space < ToRecv) {
400 #ifdef ROCKET_DEBUG_RECEIVE
401 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
402 #endif
403 if (space <= 0)
404 return;
405 ToRecv = space;
406 }
407 wRecv = ToRecv >> 1;
408 if (wRecv)
409 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
410 if (ToRecv & 1)
411 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
412 }
413 /* Push the data up to the tty layer */
414 tty_flip_buffer_push(&info->port);
415 }
416
417 /*
418 * Serial port transmit data function. Called from the timer polling loop as a
419 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
420 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
421 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
422 */
rp_do_transmit(struct r_port * info)423 static void rp_do_transmit(struct r_port *info)
424 {
425 int c;
426 CHANNEL_t *cp = &info->channel;
427 struct tty_struct *tty;
428 unsigned long flags;
429
430 #ifdef ROCKET_DEBUG_INTR
431 printk(KERN_DEBUG "%s\n", __func__);
432 #endif
433 if (!info)
434 return;
435 tty = tty_port_tty_get(&info->port);
436
437 if (tty == NULL) {
438 printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
439 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
440 return;
441 }
442
443 spin_lock_irqsave(&info->slock, flags);
444 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
445
446 /* Loop sending data to FIFO until done or FIFO full */
447 while (1) {
448 if (tty->stopped)
449 break;
450 c = min(info->xmit_fifo_room, info->xmit_cnt);
451 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
452 if (c <= 0 || info->xmit_fifo_room <= 0)
453 break;
454 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
455 if (c & 1)
456 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
457 info->xmit_tail += c;
458 info->xmit_tail &= XMIT_BUF_SIZE - 1;
459 info->xmit_cnt -= c;
460 info->xmit_fifo_room -= c;
461 #ifdef ROCKET_DEBUG_INTR
462 printk(KERN_INFO "tx %d chars...\n", c);
463 #endif
464 }
465
466 if (info->xmit_cnt == 0)
467 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
468
469 if (info->xmit_cnt < WAKEUP_CHARS) {
470 tty_wakeup(tty);
471 #ifdef ROCKETPORT_HAVE_POLL_WAIT
472 wake_up_interruptible(&tty->poll_wait);
473 #endif
474 }
475
476 spin_unlock_irqrestore(&info->slock, flags);
477 tty_kref_put(tty);
478
479 #ifdef ROCKET_DEBUG_INTR
480 printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
481 info->xmit_tail, info->xmit_fifo_room);
482 #endif
483 }
484
485 /*
486 * Called when a serial port signals it has read data in it's RX FIFO.
487 * It checks what interrupts are pending and services them, including
488 * receiving serial data.
489 */
rp_handle_port(struct r_port * info)490 static void rp_handle_port(struct r_port *info)
491 {
492 CHANNEL_t *cp;
493 unsigned int IntMask, ChanStatus;
494
495 if (!info)
496 return;
497
498 if (!tty_port_initialized(&info->port)) {
499 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
500 "info->flags & NOT_INIT\n");
501 return;
502 }
503
504 cp = &info->channel;
505
506 IntMask = sGetChanIntID(cp) & info->intmask;
507 #ifdef ROCKET_DEBUG_INTR
508 printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
509 #endif
510 ChanStatus = sGetChanStatus(cp);
511 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
512 rp_do_receive(info, cp, ChanStatus);
513 }
514 if (IntMask & DELTA_CD) { /* CD change */
515 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
516 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
517 (ChanStatus & CD_ACT) ? "on" : "off");
518 #endif
519 if (!(ChanStatus & CD_ACT) && info->cd_status) {
520 #ifdef ROCKET_DEBUG_HANGUP
521 printk(KERN_INFO "CD drop, calling hangup.\n");
522 #endif
523 tty_port_tty_hangup(&info->port, false);
524 }
525 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
526 wake_up_interruptible(&info->port.open_wait);
527 }
528 #ifdef ROCKET_DEBUG_INTR
529 if (IntMask & DELTA_CTS) { /* CTS change */
530 printk(KERN_INFO "CTS change...\n");
531 }
532 if (IntMask & DELTA_DSR) { /* DSR change */
533 printk(KERN_INFO "DSR change...\n");
534 }
535 #endif
536 }
537
538 /*
539 * The top level polling routine. Repeats every 1/100 HZ (10ms).
540 */
rp_do_poll(unsigned long dummy)541 static void rp_do_poll(unsigned long dummy)
542 {
543 CONTROLLER_t *ctlp;
544 int ctrl, aiop, ch, line;
545 unsigned int xmitmask, i;
546 unsigned int CtlMask;
547 unsigned char AiopMask;
548 Word_t bit;
549
550 /* Walk through all the boards (ctrl's) */
551 for (ctrl = 0; ctrl < max_board; ctrl++) {
552 if (rcktpt_io_addr[ctrl] <= 0)
553 continue;
554
555 /* Get a ptr to the board's control struct */
556 ctlp = sCtlNumToCtlPtr(ctrl);
557
558 /* Get the interrupt status from the board */
559 #ifdef CONFIG_PCI
560 if (ctlp->BusType == isPCI)
561 CtlMask = sPCIGetControllerIntStatus(ctlp);
562 else
563 #endif
564 CtlMask = sGetControllerIntStatus(ctlp);
565
566 /* Check if any AIOP read bits are set */
567 for (aiop = 0; CtlMask; aiop++) {
568 bit = ctlp->AiopIntrBits[aiop];
569 if (CtlMask & bit) {
570 CtlMask &= ~bit;
571 AiopMask = sGetAiopIntStatus(ctlp, aiop);
572
573 /* Check if any port read bits are set */
574 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
575 if (AiopMask & 1) {
576
577 /* Get the line number (/dev/ttyRx number). */
578 /* Read the data from the port. */
579 line = GetLineNumber(ctrl, aiop, ch);
580 rp_handle_port(rp_table[line]);
581 }
582 }
583 }
584 }
585
586 xmitmask = xmit_flags[ctrl];
587
588 /*
589 * xmit_flags contains bit-significant flags, indicating there is data
590 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
591 * 1, ... (32 total possible). The variable i has the aiop and ch
592 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
593 */
594 if (xmitmask) {
595 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
596 if (xmitmask & (1 << i)) {
597 aiop = (i & 0x18) >> 3;
598 ch = i & 0x07;
599 line = GetLineNumber(ctrl, aiop, ch);
600 rp_do_transmit(rp_table[line]);
601 }
602 }
603 }
604 }
605
606 /*
607 * Reset the timer so we get called at the next clock tick (10ms).
608 */
609 if (atomic_read(&rp_num_ports_open))
610 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
611 }
612
613 /*
614 * Initializes the r_port structure for a port, as well as enabling the port on
615 * the board.
616 * Inputs: board, aiop, chan numbers
617 */
618 static void __init
init_r_port(int board,int aiop,int chan,struct pci_dev * pci_dev)619 init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
620 {
621 unsigned rocketMode;
622 struct r_port *info;
623 int line;
624 CONTROLLER_T *ctlp;
625
626 /* Get the next available line number */
627 line = SetLineNumber(board, aiop, chan);
628
629 ctlp = sCtlNumToCtlPtr(board);
630
631 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
632 info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
633 if (!info) {
634 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
635 line);
636 return;
637 }
638
639 info->magic = RPORT_MAGIC;
640 info->line = line;
641 info->ctlp = ctlp;
642 info->board = board;
643 info->aiop = aiop;
644 info->chan = chan;
645 tty_port_init(&info->port);
646 info->port.ops = &rocket_port_ops;
647 info->flags &= ~ROCKET_MODE_MASK;
648 switch (pc104[board][line]) {
649 case 422:
650 info->flags |= ROCKET_MODE_RS422;
651 break;
652 case 485:
653 info->flags |= ROCKET_MODE_RS485;
654 break;
655 case 232:
656 default:
657 info->flags |= ROCKET_MODE_RS232;
658 break;
659 }
660
661 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
662 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
663 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
664 board, aiop, chan);
665 tty_port_destroy(&info->port);
666 kfree(info);
667 return;
668 }
669
670 rocketMode = info->flags & ROCKET_MODE_MASK;
671
672 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
673 sEnRTSToggle(&info->channel);
674 else
675 sDisRTSToggle(&info->channel);
676
677 if (ctlp->boardType == ROCKET_TYPE_PC104) {
678 switch (rocketMode) {
679 case ROCKET_MODE_RS485:
680 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
681 break;
682 case ROCKET_MODE_RS422:
683 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
684 break;
685 case ROCKET_MODE_RS232:
686 default:
687 if (info->flags & ROCKET_RTS_TOGGLE)
688 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
689 else
690 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
691 break;
692 }
693 }
694 spin_lock_init(&info->slock);
695 mutex_init(&info->write_mtx);
696 rp_table[line] = info;
697 tty_port_register_device(&info->port, rocket_driver, line,
698 pci_dev ? &pci_dev->dev : NULL);
699 }
700
701 /*
702 * Configures a rocketport port according to its termio settings. Called from
703 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
704 */
configure_r_port(struct tty_struct * tty,struct r_port * info,struct ktermios * old_termios)705 static void configure_r_port(struct tty_struct *tty, struct r_port *info,
706 struct ktermios *old_termios)
707 {
708 unsigned cflag;
709 unsigned long flags;
710 unsigned rocketMode;
711 int bits, baud, divisor;
712 CHANNEL_t *cp;
713 struct ktermios *t = &tty->termios;
714
715 cp = &info->channel;
716 cflag = t->c_cflag;
717
718 /* Byte size and parity */
719 if ((cflag & CSIZE) == CS8) {
720 sSetData8(cp);
721 bits = 10;
722 } else {
723 sSetData7(cp);
724 bits = 9;
725 }
726 if (cflag & CSTOPB) {
727 sSetStop2(cp);
728 bits++;
729 } else {
730 sSetStop1(cp);
731 }
732
733 if (cflag & PARENB) {
734 sEnParity(cp);
735 bits++;
736 if (cflag & PARODD) {
737 sSetOddParity(cp);
738 } else {
739 sSetEvenParity(cp);
740 }
741 } else {
742 sDisParity(cp);
743 }
744
745 /* baud rate */
746 baud = tty_get_baud_rate(tty);
747 if (!baud)
748 baud = 9600;
749 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
750 if ((divisor >= 8192 || divisor < 0) && old_termios) {
751 baud = tty_termios_baud_rate(old_termios);
752 if (!baud)
753 baud = 9600;
754 divisor = (rp_baud_base[info->board] / baud) - 1;
755 }
756 if (divisor >= 8192 || divisor < 0) {
757 baud = 9600;
758 divisor = (rp_baud_base[info->board] / baud) - 1;
759 }
760 info->cps = baud / bits;
761 sSetBaud(cp, divisor);
762
763 /* FIXME: Should really back compute a baud rate from the divisor */
764 tty_encode_baud_rate(tty, baud, baud);
765
766 if (cflag & CRTSCTS) {
767 info->intmask |= DELTA_CTS;
768 sEnCTSFlowCtl(cp);
769 } else {
770 info->intmask &= ~DELTA_CTS;
771 sDisCTSFlowCtl(cp);
772 }
773 if (cflag & CLOCAL) {
774 info->intmask &= ~DELTA_CD;
775 } else {
776 spin_lock_irqsave(&info->slock, flags);
777 if (sGetChanStatus(cp) & CD_ACT)
778 info->cd_status = 1;
779 else
780 info->cd_status = 0;
781 info->intmask |= DELTA_CD;
782 spin_unlock_irqrestore(&info->slock, flags);
783 }
784
785 /*
786 * Handle software flow control in the board
787 */
788 #ifdef ROCKET_SOFT_FLOW
789 if (I_IXON(tty)) {
790 sEnTxSoftFlowCtl(cp);
791 if (I_IXANY(tty)) {
792 sEnIXANY(cp);
793 } else {
794 sDisIXANY(cp);
795 }
796 sSetTxXONChar(cp, START_CHAR(tty));
797 sSetTxXOFFChar(cp, STOP_CHAR(tty));
798 } else {
799 sDisTxSoftFlowCtl(cp);
800 sDisIXANY(cp);
801 sClrTxXOFF(cp);
802 }
803 #endif
804
805 /*
806 * Set up ignore/read mask words
807 */
808 info->read_status_mask = STMRCVROVRH | 0xFF;
809 if (I_INPCK(tty))
810 info->read_status_mask |= STMFRAMEH | STMPARITYH;
811 if (I_BRKINT(tty) || I_PARMRK(tty))
812 info->read_status_mask |= STMBREAKH;
813
814 /*
815 * Characters to ignore
816 */
817 info->ignore_status_mask = 0;
818 if (I_IGNPAR(tty))
819 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
820 if (I_IGNBRK(tty)) {
821 info->ignore_status_mask |= STMBREAKH;
822 /*
823 * If we're ignoring parity and break indicators,
824 * ignore overruns too. (For real raw support).
825 */
826 if (I_IGNPAR(tty))
827 info->ignore_status_mask |= STMRCVROVRH;
828 }
829
830 rocketMode = info->flags & ROCKET_MODE_MASK;
831
832 if ((info->flags & ROCKET_RTS_TOGGLE)
833 || (rocketMode == ROCKET_MODE_RS485))
834 sEnRTSToggle(cp);
835 else
836 sDisRTSToggle(cp);
837
838 sSetRTS(&info->channel);
839
840 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
841 switch (rocketMode) {
842 case ROCKET_MODE_RS485:
843 sSetInterfaceMode(cp, InterfaceModeRS485);
844 break;
845 case ROCKET_MODE_RS422:
846 sSetInterfaceMode(cp, InterfaceModeRS422);
847 break;
848 case ROCKET_MODE_RS232:
849 default:
850 if (info->flags & ROCKET_RTS_TOGGLE)
851 sSetInterfaceMode(cp, InterfaceModeRS232T);
852 else
853 sSetInterfaceMode(cp, InterfaceModeRS232);
854 break;
855 }
856 }
857 }
858
carrier_raised(struct tty_port * port)859 static int carrier_raised(struct tty_port *port)
860 {
861 struct r_port *info = container_of(port, struct r_port, port);
862 return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
863 }
864
dtr_rts(struct tty_port * port,int on)865 static void dtr_rts(struct tty_port *port, int on)
866 {
867 struct r_port *info = container_of(port, struct r_port, port);
868 if (on) {
869 sSetDTR(&info->channel);
870 sSetRTS(&info->channel);
871 } else {
872 sClrDTR(&info->channel);
873 sClrRTS(&info->channel);
874 }
875 }
876
877 /*
878 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
879 * port's r_port struct. Initializes the port hardware.
880 */
rp_open(struct tty_struct * tty,struct file * filp)881 static int rp_open(struct tty_struct *tty, struct file *filp)
882 {
883 struct r_port *info;
884 struct tty_port *port;
885 int retval;
886 CHANNEL_t *cp;
887 unsigned long page;
888
889 info = rp_table[tty->index];
890 if (info == NULL)
891 return -ENXIO;
892 port = &info->port;
893
894 page = __get_free_page(GFP_KERNEL);
895 if (!page)
896 return -ENOMEM;
897
898 /*
899 * We must not sleep from here until the port is marked fully in use.
900 */
901 if (info->xmit_buf)
902 free_page(page);
903 else
904 info->xmit_buf = (unsigned char *) page;
905
906 tty->driver_data = info;
907 tty_port_tty_set(port, tty);
908
909 if (port->count++ == 0) {
910 atomic_inc(&rp_num_ports_open);
911
912 #ifdef ROCKET_DEBUG_OPEN
913 printk(KERN_INFO "rocket mod++ = %d...\n",
914 atomic_read(&rp_num_ports_open));
915 #endif
916 }
917 #ifdef ROCKET_DEBUG_OPEN
918 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
919 #endif
920
921 /*
922 * Info->count is now 1; so it's safe to sleep now.
923 */
924 if (!tty_port_initialized(port)) {
925 cp = &info->channel;
926 sSetRxTrigger(cp, TRIG_1);
927 if (sGetChanStatus(cp) & CD_ACT)
928 info->cd_status = 1;
929 else
930 info->cd_status = 0;
931 sDisRxStatusMode(cp);
932 sFlushRxFIFO(cp);
933 sFlushTxFIFO(cp);
934
935 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
936 sSetRxTrigger(cp, TRIG_1);
937
938 sGetChanStatus(cp);
939 sDisRxStatusMode(cp);
940 sClrTxXOFF(cp);
941
942 sDisCTSFlowCtl(cp);
943 sDisTxSoftFlowCtl(cp);
944
945 sEnRxFIFO(cp);
946 sEnTransmit(cp);
947
948 tty_port_set_initialized(&info->port, 1);
949
950 /*
951 * Set up the tty->alt_speed kludge
952 */
953 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
954 tty->alt_speed = 57600;
955 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
956 tty->alt_speed = 115200;
957 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
958 tty->alt_speed = 230400;
959 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
960 tty->alt_speed = 460800;
961
962 configure_r_port(tty, info, NULL);
963 if (C_BAUD(tty)) {
964 sSetDTR(cp);
965 sSetRTS(cp);
966 }
967 }
968 /* Starts (or resets) the maint polling loop */
969 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
970
971 retval = tty_port_block_til_ready(port, tty, filp);
972 if (retval) {
973 #ifdef ROCKET_DEBUG_OPEN
974 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
975 #endif
976 return retval;
977 }
978 return 0;
979 }
980
981 /*
982 * Exception handler that closes a serial port. info->port.count is considered critical.
983 */
rp_close(struct tty_struct * tty,struct file * filp)984 static void rp_close(struct tty_struct *tty, struct file *filp)
985 {
986 struct r_port *info = tty->driver_data;
987 struct tty_port *port = &info->port;
988 int timeout;
989 CHANNEL_t *cp;
990
991 if (rocket_paranoia_check(info, "rp_close"))
992 return;
993
994 #ifdef ROCKET_DEBUG_OPEN
995 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
996 #endif
997
998 if (tty_port_close_start(port, tty, filp) == 0)
999 return;
1000
1001 mutex_lock(&port->mutex);
1002 cp = &info->channel;
1003 /*
1004 * Before we drop DTR, make sure the UART transmitter
1005 * has completely drained; this is especially
1006 * important if there is a transmit FIFO!
1007 */
1008 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1009 if (timeout == 0)
1010 timeout = 1;
1011 rp_wait_until_sent(tty, timeout);
1012 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1013
1014 sDisTransmit(cp);
1015 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1016 sDisCTSFlowCtl(cp);
1017 sDisTxSoftFlowCtl(cp);
1018 sClrTxXOFF(cp);
1019 sFlushRxFIFO(cp);
1020 sFlushTxFIFO(cp);
1021 sClrRTS(cp);
1022 if (C_HUPCL(tty))
1023 sClrDTR(cp);
1024
1025 rp_flush_buffer(tty);
1026
1027 tty_ldisc_flush(tty);
1028
1029 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1030
1031 /* We can't yet use tty_port_close_end as the buffer handling in this
1032 driver is a bit different to the usual */
1033
1034 if (port->blocked_open) {
1035 if (port->close_delay) {
1036 msleep_interruptible(jiffies_to_msecs(port->close_delay));
1037 }
1038 wake_up_interruptible(&port->open_wait);
1039 } else {
1040 if (info->xmit_buf) {
1041 free_page((unsigned long) info->xmit_buf);
1042 info->xmit_buf = NULL;
1043 }
1044 }
1045 spin_lock_irq(&port->lock);
1046 tty->closing = 0;
1047 spin_unlock_irq(&port->lock);
1048 tty_port_set_initialized(port, 0);
1049 tty_port_set_active(port, 0);
1050 mutex_unlock(&port->mutex);
1051 tty_port_tty_set(port, NULL);
1052
1053 atomic_dec(&rp_num_ports_open);
1054
1055 #ifdef ROCKET_DEBUG_OPEN
1056 printk(KERN_INFO "rocket mod-- = %d...\n",
1057 atomic_read(&rp_num_ports_open));
1058 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1059 #endif
1060
1061 }
1062
rp_set_termios(struct tty_struct * tty,struct ktermios * old_termios)1063 static void rp_set_termios(struct tty_struct *tty,
1064 struct ktermios *old_termios)
1065 {
1066 struct r_port *info = tty->driver_data;
1067 CHANNEL_t *cp;
1068 unsigned cflag;
1069
1070 if (rocket_paranoia_check(info, "rp_set_termios"))
1071 return;
1072
1073 cflag = tty->termios.c_cflag;
1074
1075 /*
1076 * This driver doesn't support CS5 or CS6
1077 */
1078 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1079 tty->termios.c_cflag =
1080 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1081 /* Or CMSPAR */
1082 tty->termios.c_cflag &= ~CMSPAR;
1083
1084 configure_r_port(tty, info, old_termios);
1085
1086 cp = &info->channel;
1087
1088 /* Handle transition to B0 status */
1089 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
1090 sClrDTR(cp);
1091 sClrRTS(cp);
1092 }
1093
1094 /* Handle transition away from B0 status */
1095 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
1096 sSetRTS(cp);
1097 sSetDTR(cp);
1098 }
1099
1100 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty))
1101 rp_start(tty);
1102 }
1103
rp_break(struct tty_struct * tty,int break_state)1104 static int rp_break(struct tty_struct *tty, int break_state)
1105 {
1106 struct r_port *info = tty->driver_data;
1107 unsigned long flags;
1108
1109 if (rocket_paranoia_check(info, "rp_break"))
1110 return -EINVAL;
1111
1112 spin_lock_irqsave(&info->slock, flags);
1113 if (break_state == -1)
1114 sSendBreak(&info->channel);
1115 else
1116 sClrBreak(&info->channel);
1117 spin_unlock_irqrestore(&info->slock, flags);
1118 return 0;
1119 }
1120
1121 /*
1122 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1123 * the UPCI boards was added, it was decided to make this a function because
1124 * the macro was getting too complicated. All cases except the first one
1125 * (UPCIRingInd) are taken directly from the original macro.
1126 */
sGetChanRI(CHANNEL_T * ChP)1127 static int sGetChanRI(CHANNEL_T * ChP)
1128 {
1129 CONTROLLER_t *CtlP = ChP->CtlP;
1130 int ChanNum = ChP->ChanNum;
1131 int RingInd = 0;
1132
1133 if (CtlP->UPCIRingInd)
1134 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1135 else if (CtlP->AltChanRingIndicator)
1136 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1137 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1138 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1139
1140 return RingInd;
1141 }
1142
1143 /********************************************************************************************/
1144 /* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1145
1146 /*
1147 * Returns the state of the serial modem control lines. These next 2 functions
1148 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1149 */
rp_tiocmget(struct tty_struct * tty)1150 static int rp_tiocmget(struct tty_struct *tty)
1151 {
1152 struct r_port *info = tty->driver_data;
1153 unsigned int control, result, ChanStatus;
1154
1155 ChanStatus = sGetChanStatusLo(&info->channel);
1156 control = info->channel.TxControl[3];
1157 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1158 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1159 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1160 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1161 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1162 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1163
1164 return result;
1165 }
1166
1167 /*
1168 * Sets the modem control lines
1169 */
rp_tiocmset(struct tty_struct * tty,unsigned int set,unsigned int clear)1170 static int rp_tiocmset(struct tty_struct *tty,
1171 unsigned int set, unsigned int clear)
1172 {
1173 struct r_port *info = tty->driver_data;
1174
1175 if (set & TIOCM_RTS)
1176 info->channel.TxControl[3] |= SET_RTS;
1177 if (set & TIOCM_DTR)
1178 info->channel.TxControl[3] |= SET_DTR;
1179 if (clear & TIOCM_RTS)
1180 info->channel.TxControl[3] &= ~SET_RTS;
1181 if (clear & TIOCM_DTR)
1182 info->channel.TxControl[3] &= ~SET_DTR;
1183
1184 out32(info->channel.IndexAddr, info->channel.TxControl);
1185 return 0;
1186 }
1187
get_config(struct r_port * info,struct rocket_config __user * retinfo)1188 static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1189 {
1190 struct rocket_config tmp;
1191
1192 if (!retinfo)
1193 return -EFAULT;
1194 memset(&tmp, 0, sizeof (tmp));
1195 mutex_lock(&info->port.mutex);
1196 tmp.line = info->line;
1197 tmp.flags = info->flags;
1198 tmp.close_delay = info->port.close_delay;
1199 tmp.closing_wait = info->port.closing_wait;
1200 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1201 mutex_unlock(&info->port.mutex);
1202
1203 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1204 return -EFAULT;
1205 return 0;
1206 }
1207
set_config(struct tty_struct * tty,struct r_port * info,struct rocket_config __user * new_info)1208 static int set_config(struct tty_struct *tty, struct r_port *info,
1209 struct rocket_config __user *new_info)
1210 {
1211 struct rocket_config new_serial;
1212
1213 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1214 return -EFAULT;
1215
1216 mutex_lock(&info->port.mutex);
1217 if (!capable(CAP_SYS_ADMIN))
1218 {
1219 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK)) {
1220 mutex_unlock(&info->port.mutex);
1221 return -EPERM;
1222 }
1223 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1224 configure_r_port(tty, info, NULL);
1225 mutex_unlock(&info->port.mutex);
1226 return 0;
1227 }
1228
1229 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1230 info->port.close_delay = new_serial.close_delay;
1231 info->port.closing_wait = new_serial.closing_wait;
1232
1233 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1234 tty->alt_speed = 57600;
1235 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1236 tty->alt_speed = 115200;
1237 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1238 tty->alt_speed = 230400;
1239 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1240 tty->alt_speed = 460800;
1241 mutex_unlock(&info->port.mutex);
1242
1243 configure_r_port(tty, info, NULL);
1244 return 0;
1245 }
1246
1247 /*
1248 * This function fills in a rocket_ports struct with information
1249 * about what boards/ports are in the system. This info is passed
1250 * to user space. See setrocket.c where the info is used to create
1251 * the /dev/ttyRx ports.
1252 */
get_ports(struct r_port * info,struct rocket_ports __user * retports)1253 static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1254 {
1255 struct rocket_ports tmp;
1256 int board;
1257
1258 if (!retports)
1259 return -EFAULT;
1260 memset(&tmp, 0, sizeof (tmp));
1261 tmp.tty_major = rocket_driver->major;
1262
1263 for (board = 0; board < 4; board++) {
1264 tmp.rocketModel[board].model = rocketModel[board].model;
1265 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1266 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1267 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1268 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1269 }
1270 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1271 return -EFAULT;
1272 return 0;
1273 }
1274
reset_rm2(struct r_port * info,void __user * arg)1275 static int reset_rm2(struct r_port *info, void __user *arg)
1276 {
1277 int reset;
1278
1279 if (!capable(CAP_SYS_ADMIN))
1280 return -EPERM;
1281
1282 if (copy_from_user(&reset, arg, sizeof (int)))
1283 return -EFAULT;
1284 if (reset)
1285 reset = 1;
1286
1287 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1288 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1289 return -EINVAL;
1290
1291 if (info->ctlp->BusType == isISA)
1292 sModemReset(info->ctlp, info->chan, reset);
1293 else
1294 sPCIModemReset(info->ctlp, info->chan, reset);
1295
1296 return 0;
1297 }
1298
get_version(struct r_port * info,struct rocket_version __user * retvers)1299 static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1300 {
1301 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1302 return -EFAULT;
1303 return 0;
1304 }
1305
1306 /* IOCTL call handler into the driver */
rp_ioctl(struct tty_struct * tty,unsigned int cmd,unsigned long arg)1307 static int rp_ioctl(struct tty_struct *tty,
1308 unsigned int cmd, unsigned long arg)
1309 {
1310 struct r_port *info = tty->driver_data;
1311 void __user *argp = (void __user *)arg;
1312 int ret = 0;
1313
1314 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1315 return -ENXIO;
1316
1317 switch (cmd) {
1318 case RCKP_GET_STRUCT:
1319 if (copy_to_user(argp, info, sizeof (struct r_port)))
1320 ret = -EFAULT;
1321 break;
1322 case RCKP_GET_CONFIG:
1323 ret = get_config(info, argp);
1324 break;
1325 case RCKP_SET_CONFIG:
1326 ret = set_config(tty, info, argp);
1327 break;
1328 case RCKP_GET_PORTS:
1329 ret = get_ports(info, argp);
1330 break;
1331 case RCKP_RESET_RM2:
1332 ret = reset_rm2(info, argp);
1333 break;
1334 case RCKP_GET_VERSION:
1335 ret = get_version(info, argp);
1336 break;
1337 default:
1338 ret = -ENOIOCTLCMD;
1339 }
1340 return ret;
1341 }
1342
rp_send_xchar(struct tty_struct * tty,char ch)1343 static void rp_send_xchar(struct tty_struct *tty, char ch)
1344 {
1345 struct r_port *info = tty->driver_data;
1346 CHANNEL_t *cp;
1347
1348 if (rocket_paranoia_check(info, "rp_send_xchar"))
1349 return;
1350
1351 cp = &info->channel;
1352 if (sGetTxCnt(cp))
1353 sWriteTxPrioByte(cp, ch);
1354 else
1355 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1356 }
1357
rp_throttle(struct tty_struct * tty)1358 static void rp_throttle(struct tty_struct *tty)
1359 {
1360 struct r_port *info = tty->driver_data;
1361
1362 #ifdef ROCKET_DEBUG_THROTTLE
1363 printk(KERN_INFO "throttle %s ....\n", tty->name);
1364 #endif
1365
1366 if (rocket_paranoia_check(info, "rp_throttle"))
1367 return;
1368
1369 if (I_IXOFF(tty))
1370 rp_send_xchar(tty, STOP_CHAR(tty));
1371
1372 sClrRTS(&info->channel);
1373 }
1374
rp_unthrottle(struct tty_struct * tty)1375 static void rp_unthrottle(struct tty_struct *tty)
1376 {
1377 struct r_port *info = tty->driver_data;
1378 #ifdef ROCKET_DEBUG_THROTTLE
1379 printk(KERN_INFO "unthrottle %s ....\n", tty->name);
1380 #endif
1381
1382 if (rocket_paranoia_check(info, "rp_unthrottle"))
1383 return;
1384
1385 if (I_IXOFF(tty))
1386 rp_send_xchar(tty, START_CHAR(tty));
1387
1388 sSetRTS(&info->channel);
1389 }
1390
1391 /*
1392 * ------------------------------------------------------------
1393 * rp_stop() and rp_start()
1394 *
1395 * This routines are called before setting or resetting tty->stopped.
1396 * They enable or disable transmitter interrupts, as necessary.
1397 * ------------------------------------------------------------
1398 */
rp_stop(struct tty_struct * tty)1399 static void rp_stop(struct tty_struct *tty)
1400 {
1401 struct r_port *info = tty->driver_data;
1402
1403 #ifdef ROCKET_DEBUG_FLOW
1404 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1405 info->xmit_cnt, info->xmit_fifo_room);
1406 #endif
1407
1408 if (rocket_paranoia_check(info, "rp_stop"))
1409 return;
1410
1411 if (sGetTxCnt(&info->channel))
1412 sDisTransmit(&info->channel);
1413 }
1414
rp_start(struct tty_struct * tty)1415 static void rp_start(struct tty_struct *tty)
1416 {
1417 struct r_port *info = tty->driver_data;
1418
1419 #ifdef ROCKET_DEBUG_FLOW
1420 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1421 info->xmit_cnt, info->xmit_fifo_room);
1422 #endif
1423
1424 if (rocket_paranoia_check(info, "rp_stop"))
1425 return;
1426
1427 sEnTransmit(&info->channel);
1428 set_bit((info->aiop * 8) + info->chan,
1429 (void *) &xmit_flags[info->board]);
1430 }
1431
1432 /*
1433 * rp_wait_until_sent() --- wait until the transmitter is empty
1434 */
rp_wait_until_sent(struct tty_struct * tty,int timeout)1435 static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1436 {
1437 struct r_port *info = tty->driver_data;
1438 CHANNEL_t *cp;
1439 unsigned long orig_jiffies;
1440 int check_time, exit_time;
1441 int txcnt;
1442
1443 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1444 return;
1445
1446 cp = &info->channel;
1447
1448 orig_jiffies = jiffies;
1449 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1450 printk(KERN_INFO "In %s(%d) (jiff=%lu)...\n", __func__, timeout,
1451 jiffies);
1452 printk(KERN_INFO "cps=%d...\n", info->cps);
1453 #endif
1454 while (1) {
1455 txcnt = sGetTxCnt(cp);
1456 if (!txcnt) {
1457 if (sGetChanStatusLo(cp) & TXSHRMT)
1458 break;
1459 check_time = (HZ / info->cps) / 5;
1460 } else {
1461 check_time = HZ * txcnt / info->cps;
1462 }
1463 if (timeout) {
1464 exit_time = orig_jiffies + timeout - jiffies;
1465 if (exit_time <= 0)
1466 break;
1467 if (exit_time < check_time)
1468 check_time = exit_time;
1469 }
1470 if (check_time == 0)
1471 check_time = 1;
1472 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1473 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1474 jiffies, check_time);
1475 #endif
1476 msleep_interruptible(jiffies_to_msecs(check_time));
1477 if (signal_pending(current))
1478 break;
1479 }
1480 __set_current_state(TASK_RUNNING);
1481 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1482 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1483 #endif
1484 }
1485
1486 /*
1487 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1488 */
rp_hangup(struct tty_struct * tty)1489 static void rp_hangup(struct tty_struct *tty)
1490 {
1491 CHANNEL_t *cp;
1492 struct r_port *info = tty->driver_data;
1493 unsigned long flags;
1494
1495 if (rocket_paranoia_check(info, "rp_hangup"))
1496 return;
1497
1498 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1499 printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1500 #endif
1501 rp_flush_buffer(tty);
1502 spin_lock_irqsave(&info->port.lock, flags);
1503 if (info->port.count)
1504 atomic_dec(&rp_num_ports_open);
1505 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1506 spin_unlock_irqrestore(&info->port.lock, flags);
1507
1508 tty_port_hangup(&info->port);
1509
1510 cp = &info->channel;
1511 sDisRxFIFO(cp);
1512 sDisTransmit(cp);
1513 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1514 sDisCTSFlowCtl(cp);
1515 sDisTxSoftFlowCtl(cp);
1516 sClrTxXOFF(cp);
1517 tty_port_set_initialized(&info->port, 0);
1518
1519 wake_up_interruptible(&info->port.open_wait);
1520 }
1521
1522 /*
1523 * Exception handler - write char routine. The RocketPort driver uses a
1524 * double-buffering strategy, with the twist that if the in-memory CPU
1525 * buffer is empty, and there's space in the transmit FIFO, the
1526 * writing routines will write directly to transmit FIFO.
1527 * Write buffer and counters protected by spinlocks
1528 */
rp_put_char(struct tty_struct * tty,unsigned char ch)1529 static int rp_put_char(struct tty_struct *tty, unsigned char ch)
1530 {
1531 struct r_port *info = tty->driver_data;
1532 CHANNEL_t *cp;
1533 unsigned long flags;
1534
1535 if (rocket_paranoia_check(info, "rp_put_char"))
1536 return 0;
1537
1538 /*
1539 * Grab the port write mutex, locking out other processes that try to
1540 * write to this port
1541 */
1542 mutex_lock(&info->write_mtx);
1543
1544 #ifdef ROCKET_DEBUG_WRITE
1545 printk(KERN_INFO "rp_put_char %c...\n", ch);
1546 #endif
1547
1548 spin_lock_irqsave(&info->slock, flags);
1549 cp = &info->channel;
1550
1551 if (!tty->stopped && info->xmit_fifo_room == 0)
1552 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1553
1554 if (tty->stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1555 info->xmit_buf[info->xmit_head++] = ch;
1556 info->xmit_head &= XMIT_BUF_SIZE - 1;
1557 info->xmit_cnt++;
1558 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1559 } else {
1560 sOutB(sGetTxRxDataIO(cp), ch);
1561 info->xmit_fifo_room--;
1562 }
1563 spin_unlock_irqrestore(&info->slock, flags);
1564 mutex_unlock(&info->write_mtx);
1565 return 1;
1566 }
1567
1568 /*
1569 * Exception handler - write routine, called when user app writes to the device.
1570 * A per port write mutex is used to protect from another process writing to
1571 * this port at the same time. This other process could be running on the other CPU
1572 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1573 * Spinlocks protect the info xmit members.
1574 */
rp_write(struct tty_struct * tty,const unsigned char * buf,int count)1575 static int rp_write(struct tty_struct *tty,
1576 const unsigned char *buf, int count)
1577 {
1578 struct r_port *info = tty->driver_data;
1579 CHANNEL_t *cp;
1580 const unsigned char *b;
1581 int c, retval = 0;
1582 unsigned long flags;
1583
1584 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1585 return 0;
1586
1587 if (mutex_lock_interruptible(&info->write_mtx))
1588 return -ERESTARTSYS;
1589
1590 #ifdef ROCKET_DEBUG_WRITE
1591 printk(KERN_INFO "rp_write %d chars...\n", count);
1592 #endif
1593 cp = &info->channel;
1594
1595 if (!tty->stopped && info->xmit_fifo_room < count)
1596 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1597
1598 /*
1599 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1600 * into FIFO. Use the write queue for temp storage.
1601 */
1602 if (!tty->stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1603 c = min(count, info->xmit_fifo_room);
1604 b = buf;
1605
1606 /* Push data into FIFO, 2 bytes at a time */
1607 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1608
1609 /* If there is a byte remaining, write it */
1610 if (c & 1)
1611 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1612
1613 retval += c;
1614 buf += c;
1615 count -= c;
1616
1617 spin_lock_irqsave(&info->slock, flags);
1618 info->xmit_fifo_room -= c;
1619 spin_unlock_irqrestore(&info->slock, flags);
1620 }
1621
1622 /* If count is zero, we wrote it all and are done */
1623 if (!count)
1624 goto end;
1625
1626 /* Write remaining data into the port's xmit_buf */
1627 while (1) {
1628 /* Hung up ? */
1629 if (!tty_port_active(&info->port))
1630 goto end;
1631 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1632 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1633 if (c <= 0)
1634 break;
1635
1636 b = buf;
1637 memcpy(info->xmit_buf + info->xmit_head, b, c);
1638
1639 spin_lock_irqsave(&info->slock, flags);
1640 info->xmit_head =
1641 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1642 info->xmit_cnt += c;
1643 spin_unlock_irqrestore(&info->slock, flags);
1644
1645 buf += c;
1646 count -= c;
1647 retval += c;
1648 }
1649
1650 if ((retval > 0) && !tty->stopped)
1651 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1652
1653 end:
1654 if (info->xmit_cnt < WAKEUP_CHARS) {
1655 tty_wakeup(tty);
1656 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1657 wake_up_interruptible(&tty->poll_wait);
1658 #endif
1659 }
1660 mutex_unlock(&info->write_mtx);
1661 return retval;
1662 }
1663
1664 /*
1665 * Return the number of characters that can be sent. We estimate
1666 * only using the in-memory transmit buffer only, and ignore the
1667 * potential space in the transmit FIFO.
1668 */
rp_write_room(struct tty_struct * tty)1669 static int rp_write_room(struct tty_struct *tty)
1670 {
1671 struct r_port *info = tty->driver_data;
1672 int ret;
1673
1674 if (rocket_paranoia_check(info, "rp_write_room"))
1675 return 0;
1676
1677 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1678 if (ret < 0)
1679 ret = 0;
1680 #ifdef ROCKET_DEBUG_WRITE
1681 printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1682 #endif
1683 return ret;
1684 }
1685
1686 /*
1687 * Return the number of characters in the buffer. Again, this only
1688 * counts those characters in the in-memory transmit buffer.
1689 */
rp_chars_in_buffer(struct tty_struct * tty)1690 static int rp_chars_in_buffer(struct tty_struct *tty)
1691 {
1692 struct r_port *info = tty->driver_data;
1693
1694 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1695 return 0;
1696
1697 #ifdef ROCKET_DEBUG_WRITE
1698 printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1699 #endif
1700 return info->xmit_cnt;
1701 }
1702
1703 /*
1704 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1705 * r_port struct for the port. Note that spinlock are used to protect info members,
1706 * do not call this function if the spinlock is already held.
1707 */
rp_flush_buffer(struct tty_struct * tty)1708 static void rp_flush_buffer(struct tty_struct *tty)
1709 {
1710 struct r_port *info = tty->driver_data;
1711 CHANNEL_t *cp;
1712 unsigned long flags;
1713
1714 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1715 return;
1716
1717 spin_lock_irqsave(&info->slock, flags);
1718 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1719 spin_unlock_irqrestore(&info->slock, flags);
1720
1721 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1722 wake_up_interruptible(&tty->poll_wait);
1723 #endif
1724 tty_wakeup(tty);
1725
1726 cp = &info->channel;
1727 sFlushTxFIFO(cp);
1728 }
1729
1730 #ifdef CONFIG_PCI
1731
1732 static const struct pci_device_id rocket_pci_ids[] = {
1733 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4QUAD) },
1734 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8OCTA) },
1735 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8OCTA) },
1736 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8INTF) },
1737 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8INTF) },
1738 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8J) },
1739 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4J) },
1740 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8SNI) },
1741 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16SNI) },
1742 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16INTF) },
1743 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP16INTF) },
1744 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_CRP16INTF) },
1745 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP32INTF) },
1746 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP32INTF) },
1747 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP4) },
1748 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP8) },
1749 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_232) },
1750 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_422) },
1751 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP6M) },
1752 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4M) },
1753 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_8PORT) },
1754 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_4PORT) },
1755 { }
1756 };
1757 MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1758
1759 /* Resets the speaker controller on RocketModem II and III devices */
rmSpeakerReset(CONTROLLER_T * CtlP,unsigned long model)1760 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
1761 {
1762 ByteIO_t addr;
1763
1764 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
1765 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
1766 addr = CtlP->AiopIO[0] + 0x4F;
1767 sOutB(addr, 0);
1768 }
1769
1770 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
1771 if ((model == MODEL_UPCI_RM3_8PORT)
1772 || (model == MODEL_UPCI_RM3_4PORT)) {
1773 addr = CtlP->AiopIO[0] + 0x88;
1774 sOutB(addr, 0);
1775 }
1776 }
1777
1778 /***************************************************************************
1779 Function: sPCIInitController
1780 Purpose: Initialization of controller global registers and controller
1781 structure.
1782 Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
1783 IRQNum,Frequency,PeriodicOnly)
1784 CONTROLLER_T *CtlP; Ptr to controller structure
1785 int CtlNum; Controller number
1786 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
1787 This list must be in the order the AIOPs will be found on the
1788 controller. Once an AIOP in the list is not found, it is
1789 assumed that there are no more AIOPs on the controller.
1790 int AiopIOListSize; Number of addresses in AiopIOList
1791 int IRQNum; Interrupt Request number. Can be any of the following:
1792 0: Disable global interrupts
1793 3: IRQ 3
1794 4: IRQ 4
1795 5: IRQ 5
1796 9: IRQ 9
1797 10: IRQ 10
1798 11: IRQ 11
1799 12: IRQ 12
1800 15: IRQ 15
1801 Byte_t Frequency: A flag identifying the frequency
1802 of the periodic interrupt, can be any one of the following:
1803 FREQ_DIS - periodic interrupt disabled
1804 FREQ_137HZ - 137 Hertz
1805 FREQ_69HZ - 69 Hertz
1806 FREQ_34HZ - 34 Hertz
1807 FREQ_17HZ - 17 Hertz
1808 FREQ_9HZ - 9 Hertz
1809 FREQ_4HZ - 4 Hertz
1810 If IRQNum is set to 0 the Frequency parameter is
1811 overidden, it is forced to a value of FREQ_DIS.
1812 int PeriodicOnly: 1 if all interrupts except the periodic
1813 interrupt are to be blocked.
1814 0 is both the periodic interrupt and
1815 other channel interrupts are allowed.
1816 If IRQNum is set to 0 the PeriodicOnly parameter is
1817 overidden, it is forced to a value of 0.
1818 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
1819 initialization failed.
1820
1821 Comments:
1822 If periodic interrupts are to be disabled but AIOP interrupts
1823 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1824
1825 If interrupts are to be completely disabled set IRQNum to 0.
1826
1827 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1828 invalid combination.
1829
1830 This function performs initialization of global interrupt modes,
1831 but it does not actually enable global interrupts. To enable
1832 and disable global interrupts use functions sEnGlobalInt() and
1833 sDisGlobalInt(). Enabling of global interrupts is normally not
1834 done until all other initializations are complete.
1835
1836 Even if interrupts are globally enabled, they must also be
1837 individually enabled for each channel that is to generate
1838 interrupts.
1839
1840 Warnings: No range checking on any of the parameters is done.
1841
1842 No context switches are allowed while executing this function.
1843
1844 After this function all AIOPs on the controller are disabled,
1845 they can be enabled with sEnAiop().
1846 */
sPCIInitController(CONTROLLER_T * CtlP,int CtlNum,ByteIO_t * AiopIOList,int AiopIOListSize,WordIO_t ConfigIO,int IRQNum,Byte_t Frequency,int PeriodicOnly,int altChanRingIndicator,int UPCIRingInd)1847 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
1848 ByteIO_t * AiopIOList, int AiopIOListSize,
1849 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
1850 int PeriodicOnly, int altChanRingIndicator,
1851 int UPCIRingInd)
1852 {
1853 int i;
1854 ByteIO_t io;
1855
1856 CtlP->AltChanRingIndicator = altChanRingIndicator;
1857 CtlP->UPCIRingInd = UPCIRingInd;
1858 CtlP->CtlNum = CtlNum;
1859 CtlP->CtlID = CTLID_0001; /* controller release 1 */
1860 CtlP->BusType = isPCI; /* controller release 1 */
1861
1862 if (ConfigIO) {
1863 CtlP->isUPCI = 1;
1864 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
1865 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
1866 CtlP->AiopIntrBits = upci_aiop_intr_bits;
1867 } else {
1868 CtlP->isUPCI = 0;
1869 CtlP->PCIIO =
1870 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
1871 CtlP->AiopIntrBits = aiop_intr_bits;
1872 }
1873
1874 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
1875 /* Init AIOPs */
1876 CtlP->NumAiop = 0;
1877 for (i = 0; i < AiopIOListSize; i++) {
1878 io = AiopIOList[i];
1879 CtlP->AiopIO[i] = (WordIO_t) io;
1880 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
1881
1882 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
1883 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
1884 break; /* done looking for AIOPs */
1885
1886 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
1887 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
1888 sOutB(io + _INDX_DATA, sClockPrescale);
1889 CtlP->NumAiop++; /* bump count of AIOPs */
1890 }
1891
1892 if (CtlP->NumAiop == 0)
1893 return (-1);
1894 else
1895 return (CtlP->NumAiop);
1896 }
1897
1898 /*
1899 * Called when a PCI card is found. Retrieves and stores model information,
1900 * init's aiopic and serial port hardware.
1901 * Inputs: i is the board number (0-n)
1902 */
register_PCI(int i,struct pci_dev * dev)1903 static __init int register_PCI(int i, struct pci_dev *dev)
1904 {
1905 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1906 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1907 CONTROLLER_t *ctlp;
1908
1909 int fast_clock = 0;
1910 int altChanRingIndicator = 0;
1911 int ports_per_aiop = 8;
1912 WordIO_t ConfigIO = 0;
1913 ByteIO_t UPCIRingInd = 0;
1914
1915 if (!dev || !pci_match_id(rocket_pci_ids, dev) ||
1916 pci_enable_device(dev))
1917 return 0;
1918
1919 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1920
1921 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1922 rocketModel[i].loadrm2 = 0;
1923 rocketModel[i].startingPortNumber = nextLineNumber;
1924
1925 /* Depending on the model, set up some config variables */
1926 switch (dev->device) {
1927 case PCI_DEVICE_ID_RP4QUAD:
1928 max_num_aiops = 1;
1929 ports_per_aiop = 4;
1930 rocketModel[i].model = MODEL_RP4QUAD;
1931 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1932 rocketModel[i].numPorts = 4;
1933 break;
1934 case PCI_DEVICE_ID_RP8OCTA:
1935 max_num_aiops = 1;
1936 rocketModel[i].model = MODEL_RP8OCTA;
1937 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1938 rocketModel[i].numPorts = 8;
1939 break;
1940 case PCI_DEVICE_ID_URP8OCTA:
1941 max_num_aiops = 1;
1942 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1943 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1944 rocketModel[i].numPorts = 8;
1945 break;
1946 case PCI_DEVICE_ID_RP8INTF:
1947 max_num_aiops = 1;
1948 rocketModel[i].model = MODEL_RP8INTF;
1949 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1950 rocketModel[i].numPorts = 8;
1951 break;
1952 case PCI_DEVICE_ID_URP8INTF:
1953 max_num_aiops = 1;
1954 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1955 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1956 rocketModel[i].numPorts = 8;
1957 break;
1958 case PCI_DEVICE_ID_RP8J:
1959 max_num_aiops = 1;
1960 rocketModel[i].model = MODEL_RP8J;
1961 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1962 rocketModel[i].numPorts = 8;
1963 break;
1964 case PCI_DEVICE_ID_RP4J:
1965 max_num_aiops = 1;
1966 ports_per_aiop = 4;
1967 rocketModel[i].model = MODEL_RP4J;
1968 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1969 rocketModel[i].numPorts = 4;
1970 break;
1971 case PCI_DEVICE_ID_RP8SNI:
1972 max_num_aiops = 1;
1973 rocketModel[i].model = MODEL_RP8SNI;
1974 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1975 rocketModel[i].numPorts = 8;
1976 break;
1977 case PCI_DEVICE_ID_RP16SNI:
1978 max_num_aiops = 2;
1979 rocketModel[i].model = MODEL_RP16SNI;
1980 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1981 rocketModel[i].numPorts = 16;
1982 break;
1983 case PCI_DEVICE_ID_RP16INTF:
1984 max_num_aiops = 2;
1985 rocketModel[i].model = MODEL_RP16INTF;
1986 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1987 rocketModel[i].numPorts = 16;
1988 break;
1989 case PCI_DEVICE_ID_URP16INTF:
1990 max_num_aiops = 2;
1991 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1992 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1993 rocketModel[i].numPorts = 16;
1994 break;
1995 case PCI_DEVICE_ID_CRP16INTF:
1996 max_num_aiops = 2;
1997 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1998 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1999 rocketModel[i].numPorts = 16;
2000 break;
2001 case PCI_DEVICE_ID_RP32INTF:
2002 max_num_aiops = 4;
2003 rocketModel[i].model = MODEL_RP32INTF;
2004 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
2005 rocketModel[i].numPorts = 32;
2006 break;
2007 case PCI_DEVICE_ID_URP32INTF:
2008 max_num_aiops = 4;
2009 rocketModel[i].model = MODEL_UPCI_RP32INTF;
2010 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
2011 rocketModel[i].numPorts = 32;
2012 break;
2013 case PCI_DEVICE_ID_RPP4:
2014 max_num_aiops = 1;
2015 ports_per_aiop = 4;
2016 altChanRingIndicator++;
2017 fast_clock++;
2018 rocketModel[i].model = MODEL_RPP4;
2019 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
2020 rocketModel[i].numPorts = 4;
2021 break;
2022 case PCI_DEVICE_ID_RPP8:
2023 max_num_aiops = 2;
2024 ports_per_aiop = 4;
2025 altChanRingIndicator++;
2026 fast_clock++;
2027 rocketModel[i].model = MODEL_RPP8;
2028 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2029 rocketModel[i].numPorts = 8;
2030 break;
2031 case PCI_DEVICE_ID_RP2_232:
2032 max_num_aiops = 1;
2033 ports_per_aiop = 2;
2034 altChanRingIndicator++;
2035 fast_clock++;
2036 rocketModel[i].model = MODEL_RP2_232;
2037 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2038 rocketModel[i].numPorts = 2;
2039 break;
2040 case PCI_DEVICE_ID_RP2_422:
2041 max_num_aiops = 1;
2042 ports_per_aiop = 2;
2043 altChanRingIndicator++;
2044 fast_clock++;
2045 rocketModel[i].model = MODEL_RP2_422;
2046 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2047 rocketModel[i].numPorts = 2;
2048 break;
2049 case PCI_DEVICE_ID_RP6M:
2050
2051 max_num_aiops = 1;
2052 ports_per_aiop = 6;
2053
2054 /* If revision is 1, the rocketmodem flash must be loaded.
2055 * If it is 2 it is a "socketed" version. */
2056 if (dev->revision == 1) {
2057 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2058 rocketModel[i].loadrm2 = 1;
2059 } else {
2060 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2061 }
2062
2063 rocketModel[i].model = MODEL_RP6M;
2064 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2065 rocketModel[i].numPorts = 6;
2066 break;
2067 case PCI_DEVICE_ID_RP4M:
2068 max_num_aiops = 1;
2069 ports_per_aiop = 4;
2070 if (dev->revision == 1) {
2071 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2072 rocketModel[i].loadrm2 = 1;
2073 } else {
2074 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2075 }
2076
2077 rocketModel[i].model = MODEL_RP4M;
2078 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2079 rocketModel[i].numPorts = 4;
2080 break;
2081 default:
2082 max_num_aiops = 0;
2083 break;
2084 }
2085
2086 /*
2087 * Check for UPCI boards.
2088 */
2089
2090 switch (dev->device) {
2091 case PCI_DEVICE_ID_URP32INTF:
2092 case PCI_DEVICE_ID_URP8INTF:
2093 case PCI_DEVICE_ID_URP16INTF:
2094 case PCI_DEVICE_ID_CRP16INTF:
2095 case PCI_DEVICE_ID_URP8OCTA:
2096 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2097 ConfigIO = pci_resource_start(dev, 1);
2098 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2099 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2100
2101 /*
2102 * Check for octa or quad cable.
2103 */
2104 if (!
2105 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2106 PCI_GPIO_CTRL_8PORT)) {
2107 ports_per_aiop = 4;
2108 rocketModel[i].numPorts = 4;
2109 }
2110 }
2111 break;
2112 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2113 max_num_aiops = 1;
2114 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2115 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2116 rocketModel[i].numPorts = 8;
2117 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2118 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2119 ConfigIO = pci_resource_start(dev, 1);
2120 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2121 break;
2122 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2123 max_num_aiops = 1;
2124 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2125 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2126 rocketModel[i].numPorts = 4;
2127 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2128 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2129 ConfigIO = pci_resource_start(dev, 1);
2130 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2131 break;
2132 default:
2133 break;
2134 }
2135
2136 if (fast_clock) {
2137 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2138 rp_baud_base[i] = 921600;
2139 } else {
2140 /*
2141 * If support_low_speed is set, use the slow clock
2142 * prescale, which supports 50 bps
2143 */
2144 if (support_low_speed) {
2145 /* mod 9 (divide by 10) prescale */
2146 sClockPrescale = 0x19;
2147 rp_baud_base[i] = 230400;
2148 } else {
2149 /* mod 4 (divide by 5) prescale */
2150 sClockPrescale = 0x14;
2151 rp_baud_base[i] = 460800;
2152 }
2153 }
2154
2155 for (aiop = 0; aiop < max_num_aiops; aiop++)
2156 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2157 ctlp = sCtlNumToCtlPtr(i);
2158 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2159 for (aiop = 0; aiop < max_num_aiops; aiop++)
2160 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2161
2162 dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2163 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2164 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2165 rocketModel[i].startingPortNumber,
2166 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
2167
2168 if (num_aiops <= 0) {
2169 rcktpt_io_addr[i] = 0;
2170 return (0);
2171 }
2172 is_PCI[i] = 1;
2173
2174 /* Reset the AIOPIC, init the serial ports */
2175 for (aiop = 0; aiop < num_aiops; aiop++) {
2176 sResetAiopByNum(ctlp, aiop);
2177 num_chan = ports_per_aiop;
2178 for (chan = 0; chan < num_chan; chan++)
2179 init_r_port(i, aiop, chan, dev);
2180 }
2181
2182 /* Rocket modems must be reset */
2183 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2184 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2185 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2186 num_chan = ports_per_aiop;
2187 for (chan = 0; chan < num_chan; chan++)
2188 sPCIModemReset(ctlp, chan, 1);
2189 msleep(500);
2190 for (chan = 0; chan < num_chan; chan++)
2191 sPCIModemReset(ctlp, chan, 0);
2192 msleep(500);
2193 rmSpeakerReset(ctlp, rocketModel[i].model);
2194 }
2195 return (1);
2196 }
2197
2198 /*
2199 * Probes for PCI cards, inits them if found
2200 * Input: board_found = number of ISA boards already found, or the
2201 * starting board number
2202 * Returns: Number of PCI boards found
2203 */
init_PCI(int boards_found)2204 static int __init init_PCI(int boards_found)
2205 {
2206 struct pci_dev *dev = NULL;
2207 int count = 0;
2208
2209 /* Work through the PCI device list, pulling out ours */
2210 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2211 if (register_PCI(count + boards_found, dev))
2212 count++;
2213 }
2214 return (count);
2215 }
2216
2217 #endif /* CONFIG_PCI */
2218
2219 /*
2220 * Probes for ISA cards
2221 * Input: i = the board number to look for
2222 * Returns: 1 if board found, 0 else
2223 */
init_ISA(int i)2224 static int __init init_ISA(int i)
2225 {
2226 int num_aiops, num_chan = 0, total_num_chan = 0;
2227 int aiop, chan;
2228 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2229 CONTROLLER_t *ctlp;
2230 char *type_string;
2231
2232 /* If io_addr is zero, no board configured */
2233 if (rcktpt_io_addr[i] == 0)
2234 return (0);
2235
2236 /* Reserve the IO region */
2237 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2238 printk(KERN_ERR "Unable to reserve IO region for configured "
2239 "ISA RocketPort at address 0x%lx, board not "
2240 "installed...\n", rcktpt_io_addr[i]);
2241 rcktpt_io_addr[i] = 0;
2242 return (0);
2243 }
2244
2245 ctlp = sCtlNumToCtlPtr(i);
2246
2247 ctlp->boardType = rcktpt_type[i];
2248
2249 switch (rcktpt_type[i]) {
2250 case ROCKET_TYPE_PC104:
2251 type_string = "(PC104)";
2252 break;
2253 case ROCKET_TYPE_MODEM:
2254 type_string = "(RocketModem)";
2255 break;
2256 case ROCKET_TYPE_MODEMII:
2257 type_string = "(RocketModem II)";
2258 break;
2259 default:
2260 type_string = "";
2261 break;
2262 }
2263
2264 /*
2265 * If support_low_speed is set, use the slow clock prescale,
2266 * which supports 50 bps
2267 */
2268 if (support_low_speed) {
2269 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2270 rp_baud_base[i] = 230400;
2271 } else {
2272 sClockPrescale = 0x14; /* mod 4 (divide by 5) prescale */
2273 rp_baud_base[i] = 460800;
2274 }
2275
2276 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2277 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2278
2279 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2280
2281 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2282 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2283 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2284 }
2285
2286 /* If something went wrong initing the AIOP's release the ISA IO memory */
2287 if (num_aiops <= 0) {
2288 release_region(rcktpt_io_addr[i], 64);
2289 rcktpt_io_addr[i] = 0;
2290 return (0);
2291 }
2292
2293 rocketModel[i].startingPortNumber = nextLineNumber;
2294
2295 for (aiop = 0; aiop < num_aiops; aiop++) {
2296 sResetAiopByNum(ctlp, aiop);
2297 sEnAiop(ctlp, aiop);
2298 num_chan = sGetAiopNumChan(ctlp, aiop);
2299 total_num_chan += num_chan;
2300 for (chan = 0; chan < num_chan; chan++)
2301 init_r_port(i, aiop, chan, NULL);
2302 }
2303 is_PCI[i] = 0;
2304 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2305 num_chan = sGetAiopNumChan(ctlp, 0);
2306 total_num_chan = num_chan;
2307 for (chan = 0; chan < num_chan; chan++)
2308 sModemReset(ctlp, chan, 1);
2309 msleep(500);
2310 for (chan = 0; chan < num_chan; chan++)
2311 sModemReset(ctlp, chan, 0);
2312 msleep(500);
2313 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2314 } else {
2315 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2316 }
2317 rocketModel[i].numPorts = total_num_chan;
2318 rocketModel[i].model = MODEL_ISA;
2319
2320 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2321 i, rcktpt_io_addr[i], num_aiops, type_string);
2322
2323 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2324 rocketModel[i].modelString,
2325 rocketModel[i].startingPortNumber,
2326 rocketModel[i].startingPortNumber +
2327 rocketModel[i].numPorts - 1);
2328
2329 return (1);
2330 }
2331
2332 static const struct tty_operations rocket_ops = {
2333 .open = rp_open,
2334 .close = rp_close,
2335 .write = rp_write,
2336 .put_char = rp_put_char,
2337 .write_room = rp_write_room,
2338 .chars_in_buffer = rp_chars_in_buffer,
2339 .flush_buffer = rp_flush_buffer,
2340 .ioctl = rp_ioctl,
2341 .throttle = rp_throttle,
2342 .unthrottle = rp_unthrottle,
2343 .set_termios = rp_set_termios,
2344 .stop = rp_stop,
2345 .start = rp_start,
2346 .hangup = rp_hangup,
2347 .break_ctl = rp_break,
2348 .send_xchar = rp_send_xchar,
2349 .wait_until_sent = rp_wait_until_sent,
2350 .tiocmget = rp_tiocmget,
2351 .tiocmset = rp_tiocmset,
2352 };
2353
2354 static const struct tty_port_operations rocket_port_ops = {
2355 .carrier_raised = carrier_raised,
2356 .dtr_rts = dtr_rts,
2357 };
2358
2359 /*
2360 * The module "startup" routine; it's run when the module is loaded.
2361 */
rp_init(void)2362 static int __init rp_init(void)
2363 {
2364 int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
2365
2366 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2367 ROCKET_VERSION, ROCKET_DATE);
2368
2369 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2370 if (!rocket_driver)
2371 goto err;
2372
2373 /*
2374 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2375 * zero, use the default controller IO address of board1 + 0x40.
2376 */
2377 if (board1) {
2378 if (controller == 0)
2379 controller = board1 + 0x40;
2380 } else {
2381 controller = 0; /* Used as a flag, meaning no ISA boards */
2382 }
2383
2384 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2385 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2386 printk(KERN_ERR "Unable to reserve IO region for first "
2387 "configured ISA RocketPort controller 0x%lx. "
2388 "Driver exiting\n", controller);
2389 ret = -EBUSY;
2390 goto err_tty;
2391 }
2392
2393 /* Store ISA variable retrieved from command line or .conf file. */
2394 rcktpt_io_addr[0] = board1;
2395 rcktpt_io_addr[1] = board2;
2396 rcktpt_io_addr[2] = board3;
2397 rcktpt_io_addr[3] = board4;
2398
2399 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2400 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2401 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2402 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2403 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2404 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2405 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2406 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2407
2408 /*
2409 * Set up the tty driver structure and then register this
2410 * driver with the tty layer.
2411 */
2412
2413 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
2414 rocket_driver->name = "ttyR";
2415 rocket_driver->driver_name = "Comtrol RocketPort";
2416 rocket_driver->major = TTY_ROCKET_MAJOR;
2417 rocket_driver->minor_start = 0;
2418 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2419 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2420 rocket_driver->init_termios = tty_std_termios;
2421 rocket_driver->init_termios.c_cflag =
2422 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2423 rocket_driver->init_termios.c_ispeed = 9600;
2424 rocket_driver->init_termios.c_ospeed = 9600;
2425 #ifdef ROCKET_SOFT_FLOW
2426 rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
2427 #endif
2428 tty_set_operations(rocket_driver, &rocket_ops);
2429
2430 ret = tty_register_driver(rocket_driver);
2431 if (ret < 0) {
2432 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2433 goto err_controller;
2434 }
2435
2436 #ifdef ROCKET_DEBUG_OPEN
2437 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2438 #endif
2439
2440 /*
2441 * OK, let's probe each of the controllers looking for boards. Any boards found
2442 * will be initialized here.
2443 */
2444 isa_boards_found = 0;
2445 pci_boards_found = 0;
2446
2447 for (i = 0; i < NUM_BOARDS; i++) {
2448 if (init_ISA(i))
2449 isa_boards_found++;
2450 }
2451
2452 #ifdef CONFIG_PCI
2453 if (isa_boards_found < NUM_BOARDS)
2454 pci_boards_found = init_PCI(isa_boards_found);
2455 #endif
2456
2457 max_board = pci_boards_found + isa_boards_found;
2458
2459 if (max_board == 0) {
2460 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2461 ret = -ENXIO;
2462 goto err_ttyu;
2463 }
2464
2465 return 0;
2466 err_ttyu:
2467 tty_unregister_driver(rocket_driver);
2468 err_controller:
2469 if (controller)
2470 release_region(controller, 4);
2471 err_tty:
2472 put_tty_driver(rocket_driver);
2473 err:
2474 return ret;
2475 }
2476
2477
rp_cleanup_module(void)2478 static void rp_cleanup_module(void)
2479 {
2480 int retval;
2481 int i;
2482
2483 del_timer_sync(&rocket_timer);
2484
2485 retval = tty_unregister_driver(rocket_driver);
2486 if (retval)
2487 printk(KERN_ERR "Error %d while trying to unregister "
2488 "rocketport driver\n", -retval);
2489
2490 for (i = 0; i < MAX_RP_PORTS; i++)
2491 if (rp_table[i]) {
2492 tty_unregister_device(rocket_driver, i);
2493 tty_port_destroy(&rp_table[i]->port);
2494 kfree(rp_table[i]);
2495 }
2496
2497 put_tty_driver(rocket_driver);
2498
2499 for (i = 0; i < NUM_BOARDS; i++) {
2500 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2501 continue;
2502 release_region(rcktpt_io_addr[i], 64);
2503 }
2504 if (controller)
2505 release_region(controller, 4);
2506 }
2507
2508 /***************************************************************************
2509 Function: sInitController
2510 Purpose: Initialization of controller global registers and controller
2511 structure.
2512 Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2513 IRQNum,Frequency,PeriodicOnly)
2514 CONTROLLER_T *CtlP; Ptr to controller structure
2515 int CtlNum; Controller number
2516 ByteIO_t MudbacIO; Mudbac base I/O address.
2517 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2518 This list must be in the order the AIOPs will be found on the
2519 controller. Once an AIOP in the list is not found, it is
2520 assumed that there are no more AIOPs on the controller.
2521 int AiopIOListSize; Number of addresses in AiopIOList
2522 int IRQNum; Interrupt Request number. Can be any of the following:
2523 0: Disable global interrupts
2524 3: IRQ 3
2525 4: IRQ 4
2526 5: IRQ 5
2527 9: IRQ 9
2528 10: IRQ 10
2529 11: IRQ 11
2530 12: IRQ 12
2531 15: IRQ 15
2532 Byte_t Frequency: A flag identifying the frequency
2533 of the periodic interrupt, can be any one of the following:
2534 FREQ_DIS - periodic interrupt disabled
2535 FREQ_137HZ - 137 Hertz
2536 FREQ_69HZ - 69 Hertz
2537 FREQ_34HZ - 34 Hertz
2538 FREQ_17HZ - 17 Hertz
2539 FREQ_9HZ - 9 Hertz
2540 FREQ_4HZ - 4 Hertz
2541 If IRQNum is set to 0 the Frequency parameter is
2542 overidden, it is forced to a value of FREQ_DIS.
2543 int PeriodicOnly: 1 if all interrupts except the periodic
2544 interrupt are to be blocked.
2545 0 is both the periodic interrupt and
2546 other channel interrupts are allowed.
2547 If IRQNum is set to 0 the PeriodicOnly parameter is
2548 overidden, it is forced to a value of 0.
2549 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2550 initialization failed.
2551
2552 Comments:
2553 If periodic interrupts are to be disabled but AIOP interrupts
2554 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2555
2556 If interrupts are to be completely disabled set IRQNum to 0.
2557
2558 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2559 invalid combination.
2560
2561 This function performs initialization of global interrupt modes,
2562 but it does not actually enable global interrupts. To enable
2563 and disable global interrupts use functions sEnGlobalInt() and
2564 sDisGlobalInt(). Enabling of global interrupts is normally not
2565 done until all other initializations are complete.
2566
2567 Even if interrupts are globally enabled, they must also be
2568 individually enabled for each channel that is to generate
2569 interrupts.
2570
2571 Warnings: No range checking on any of the parameters is done.
2572
2573 No context switches are allowed while executing this function.
2574
2575 After this function all AIOPs on the controller are disabled,
2576 they can be enabled with sEnAiop().
2577 */
sInitController(CONTROLLER_T * CtlP,int CtlNum,ByteIO_t MudbacIO,ByteIO_t * AiopIOList,int AiopIOListSize,int IRQNum,Byte_t Frequency,int PeriodicOnly)2578 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2579 ByteIO_t * AiopIOList, int AiopIOListSize,
2580 int IRQNum, Byte_t Frequency, int PeriodicOnly)
2581 {
2582 int i;
2583 ByteIO_t io;
2584 int done;
2585
2586 CtlP->AiopIntrBits = aiop_intr_bits;
2587 CtlP->AltChanRingIndicator = 0;
2588 CtlP->CtlNum = CtlNum;
2589 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2590 CtlP->BusType = isISA;
2591 CtlP->MBaseIO = MudbacIO;
2592 CtlP->MReg1IO = MudbacIO + 1;
2593 CtlP->MReg2IO = MudbacIO + 2;
2594 CtlP->MReg3IO = MudbacIO + 3;
2595 #if 1
2596 CtlP->MReg2 = 0; /* interrupt disable */
2597 CtlP->MReg3 = 0; /* no periodic interrupts */
2598 #else
2599 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2600 CtlP->MReg2 = 0; /* interrupt disable */
2601 CtlP->MReg3 = 0; /* no periodic interrupts */
2602 } else {
2603 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2604 CtlP->MReg3 = Frequency; /* set frequency */
2605 if (PeriodicOnly) { /* periodic interrupt only */
2606 CtlP->MReg3 |= PERIODIC_ONLY;
2607 }
2608 }
2609 #endif
2610 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2611 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2612 sControllerEOI(CtlP); /* clear EOI if warm init */
2613 /* Init AIOPs */
2614 CtlP->NumAiop = 0;
2615 for (i = done = 0; i < AiopIOListSize; i++) {
2616 io = AiopIOList[i];
2617 CtlP->AiopIO[i] = (WordIO_t) io;
2618 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2619 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2620 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2621 if (done)
2622 continue;
2623 sEnAiop(CtlP, i); /* enable the AIOP */
2624 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2625 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2626 done = 1; /* done looking for AIOPs */
2627 else {
2628 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2629 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2630 sOutB(io + _INDX_DATA, sClockPrescale);
2631 CtlP->NumAiop++; /* bump count of AIOPs */
2632 }
2633 sDisAiop(CtlP, i); /* disable AIOP */
2634 }
2635
2636 if (CtlP->NumAiop == 0)
2637 return (-1);
2638 else
2639 return (CtlP->NumAiop);
2640 }
2641
2642 /***************************************************************************
2643 Function: sReadAiopID
2644 Purpose: Read the AIOP idenfication number directly from an AIOP.
2645 Call: sReadAiopID(io)
2646 ByteIO_t io: AIOP base I/O address
2647 Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2648 is replace by an identifying number.
2649 Flag AIOPID_NULL if no valid AIOP is found
2650 Warnings: No context switches are allowed while executing this function.
2651
2652 */
sReadAiopID(ByteIO_t io)2653 static int sReadAiopID(ByteIO_t io)
2654 {
2655 Byte_t AiopID; /* ID byte from AIOP */
2656
2657 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2658 sOutB(io + _CMD_REG, 0x0);
2659 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2660 if (AiopID == 0x06)
2661 return (1);
2662 else /* AIOP does not exist */
2663 return (-1);
2664 }
2665
2666 /***************************************************************************
2667 Function: sReadAiopNumChan
2668 Purpose: Read the number of channels available in an AIOP directly from
2669 an AIOP.
2670 Call: sReadAiopNumChan(io)
2671 WordIO_t io: AIOP base I/O address
2672 Return: int: The number of channels available
2673 Comments: The number of channels is determined by write/reads from identical
2674 offsets within the SRAM address spaces for channels 0 and 4.
2675 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2676 AIOP, otherwise it is an 8 channel.
2677 Warnings: No context switches are allowed while executing this function.
2678 */
sReadAiopNumChan(WordIO_t io)2679 static int sReadAiopNumChan(WordIO_t io)
2680 {
2681 Word_t x;
2682 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2683
2684 /* write to chan 0 SRAM */
2685 out32((DWordIO_t) io + _INDX_ADDR, R);
2686 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2687 x = sInW(io + _INDX_DATA);
2688 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2689 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2690 return (8);
2691 else
2692 return (4);
2693 }
2694
2695 /***************************************************************************
2696 Function: sInitChan
2697 Purpose: Initialization of a channel and channel structure
2698 Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2699 CONTROLLER_T *CtlP; Ptr to controller structure
2700 CHANNEL_T *ChP; Ptr to channel structure
2701 int AiopNum; AIOP number within controller
2702 int ChanNum; Channel number within AIOP
2703 Return: int: 1 if initialization succeeded, 0 if it fails because channel
2704 number exceeds number of channels available in AIOP.
2705 Comments: This function must be called before a channel can be used.
2706 Warnings: No range checking on any of the parameters is done.
2707
2708 No context switches are allowed while executing this function.
2709 */
sInitChan(CONTROLLER_T * CtlP,CHANNEL_T * ChP,int AiopNum,int ChanNum)2710 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2711 int ChanNum)
2712 {
2713 int i;
2714 WordIO_t AiopIO;
2715 WordIO_t ChIOOff;
2716 Byte_t *ChR;
2717 Word_t ChOff;
2718 static Byte_t R[4];
2719 int brd9600;
2720
2721 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2722 return 0; /* exceeds num chans in AIOP */
2723
2724 /* Channel, AIOP, and controller identifiers */
2725 ChP->CtlP = CtlP;
2726 ChP->ChanID = CtlP->AiopID[AiopNum];
2727 ChP->AiopNum = AiopNum;
2728 ChP->ChanNum = ChanNum;
2729
2730 /* Global direct addresses */
2731 AiopIO = CtlP->AiopIO[AiopNum];
2732 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2733 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2734 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2735 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2736 ChP->IndexData = AiopIO + _INDX_DATA;
2737
2738 /* Channel direct addresses */
2739 ChIOOff = AiopIO + ChP->ChanNum * 2;
2740 ChP->TxRxData = ChIOOff + _TD0;
2741 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2742 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2743 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2744
2745 /* Initialize the channel from the RData array */
2746 for (i = 0; i < RDATASIZE; i += 4) {
2747 R[0] = RData[i];
2748 R[1] = RData[i + 1] + 0x10 * ChanNum;
2749 R[2] = RData[i + 2];
2750 R[3] = RData[i + 3];
2751 out32(ChP->IndexAddr, R);
2752 }
2753
2754 ChR = ChP->R;
2755 for (i = 0; i < RREGDATASIZE; i += 4) {
2756 ChR[i] = RRegData[i];
2757 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2758 ChR[i + 2] = RRegData[i + 2];
2759 ChR[i + 3] = RRegData[i + 3];
2760 }
2761
2762 /* Indexed registers */
2763 ChOff = (Word_t) ChanNum *0x1000;
2764
2765 if (sClockPrescale == 0x14)
2766 brd9600 = 47;
2767 else
2768 brd9600 = 23;
2769
2770 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2771 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2772 ChP->BaudDiv[2] = (Byte_t) brd9600;
2773 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2774 out32(ChP->IndexAddr, ChP->BaudDiv);
2775
2776 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2777 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2778 ChP->TxControl[2] = 0;
2779 ChP->TxControl[3] = 0;
2780 out32(ChP->IndexAddr, ChP->TxControl);
2781
2782 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2783 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2784 ChP->RxControl[2] = 0;
2785 ChP->RxControl[3] = 0;
2786 out32(ChP->IndexAddr, ChP->RxControl);
2787
2788 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2789 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2790 ChP->TxEnables[2] = 0;
2791 ChP->TxEnables[3] = 0;
2792 out32(ChP->IndexAddr, ChP->TxEnables);
2793
2794 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2795 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2796 ChP->TxCompare[2] = 0;
2797 ChP->TxCompare[3] = 0;
2798 out32(ChP->IndexAddr, ChP->TxCompare);
2799
2800 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2801 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2802 ChP->TxReplace1[2] = 0;
2803 ChP->TxReplace1[3] = 0;
2804 out32(ChP->IndexAddr, ChP->TxReplace1);
2805
2806 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2807 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2808 ChP->TxReplace2[2] = 0;
2809 ChP->TxReplace2[3] = 0;
2810 out32(ChP->IndexAddr, ChP->TxReplace2);
2811
2812 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2813 ChP->TxFIFO = ChOff + _TX_FIFO;
2814
2815 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2816 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2817 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2818 sOutW(ChP->IndexData, 0);
2819 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2820 ChP->RxFIFO = ChOff + _RX_FIFO;
2821
2822 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2823 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2824 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2825 sOutW(ChP->IndexData, 0);
2826 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2827 sOutW(ChP->IndexData, 0);
2828 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2829 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2830 sOutB(ChP->IndexData, 0);
2831 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2832 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2833 sOutB(ChP->IndexData, 0);
2834 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2835 sEnRxProcessor(ChP); /* start the Rx processor */
2836
2837 return 1;
2838 }
2839
2840 /***************************************************************************
2841 Function: sStopRxProcessor
2842 Purpose: Stop the receive processor from processing a channel.
2843 Call: sStopRxProcessor(ChP)
2844 CHANNEL_T *ChP; Ptr to channel structure
2845
2846 Comments: The receive processor can be started again with sStartRxProcessor().
2847 This function causes the receive processor to skip over the
2848 stopped channel. It does not stop it from processing other channels.
2849
2850 Warnings: No context switches are allowed while executing this function.
2851
2852 Do not leave the receive processor stopped for more than one
2853 character time.
2854
2855 After calling this function a delay of 4 uS is required to ensure
2856 that the receive processor is no longer processing this channel.
2857 */
sStopRxProcessor(CHANNEL_T * ChP)2858 static void sStopRxProcessor(CHANNEL_T * ChP)
2859 {
2860 Byte_t R[4];
2861
2862 R[0] = ChP->R[0];
2863 R[1] = ChP->R[1];
2864 R[2] = 0x0a;
2865 R[3] = ChP->R[3];
2866 out32(ChP->IndexAddr, R);
2867 }
2868
2869 /***************************************************************************
2870 Function: sFlushRxFIFO
2871 Purpose: Flush the Rx FIFO
2872 Call: sFlushRxFIFO(ChP)
2873 CHANNEL_T *ChP; Ptr to channel structure
2874 Return: void
2875 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2876 while it is being flushed the receive processor is stopped
2877 and the transmitter is disabled. After these operations a
2878 4 uS delay is done before clearing the pointers to allow
2879 the receive processor to stop. These items are handled inside
2880 this function.
2881 Warnings: No context switches are allowed while executing this function.
2882 */
sFlushRxFIFO(CHANNEL_T * ChP)2883 static void sFlushRxFIFO(CHANNEL_T * ChP)
2884 {
2885 int i;
2886 Byte_t Ch; /* channel number within AIOP */
2887 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
2888
2889 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
2890 return; /* don't need to flush */
2891
2892 RxFIFOEnabled = 0;
2893 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
2894 RxFIFOEnabled = 1;
2895 sDisRxFIFO(ChP); /* disable it */
2896 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
2897 sInB(ChP->IntChan); /* depends on bus i/o timing */
2898 }
2899 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
2900 Ch = (Byte_t) sGetChanNum(ChP);
2901 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
2902 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
2903 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2904 sOutW(ChP->IndexData, 0);
2905 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2906 sOutW(ChP->IndexData, 0);
2907 if (RxFIFOEnabled)
2908 sEnRxFIFO(ChP); /* enable Rx FIFO */
2909 }
2910
2911 /***************************************************************************
2912 Function: sFlushTxFIFO
2913 Purpose: Flush the Tx FIFO
2914 Call: sFlushTxFIFO(ChP)
2915 CHANNEL_T *ChP; Ptr to channel structure
2916 Return: void
2917 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2918 while it is being flushed the receive processor is stopped
2919 and the transmitter is disabled. After these operations a
2920 4 uS delay is done before clearing the pointers to allow
2921 the receive processor to stop. These items are handled inside
2922 this function.
2923 Warnings: No context switches are allowed while executing this function.
2924 */
sFlushTxFIFO(CHANNEL_T * ChP)2925 static void sFlushTxFIFO(CHANNEL_T * ChP)
2926 {
2927 int i;
2928 Byte_t Ch; /* channel number within AIOP */
2929 int TxEnabled; /* 1 if transmitter enabled */
2930
2931 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
2932 return; /* don't need to flush */
2933
2934 TxEnabled = 0;
2935 if (ChP->TxControl[3] & TX_ENABLE) {
2936 TxEnabled = 1;
2937 sDisTransmit(ChP); /* disable transmitter */
2938 }
2939 sStopRxProcessor(ChP); /* stop Rx processor */
2940 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
2941 sInB(ChP->IntChan); /* depends on bus i/o timing */
2942 Ch = (Byte_t) sGetChanNum(ChP);
2943 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
2944 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
2945 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2946 sOutW(ChP->IndexData, 0);
2947 if (TxEnabled)
2948 sEnTransmit(ChP); /* enable transmitter */
2949 sStartRxProcessor(ChP); /* restart Rx processor */
2950 }
2951
2952 /***************************************************************************
2953 Function: sWriteTxPrioByte
2954 Purpose: Write a byte of priority transmit data to a channel
2955 Call: sWriteTxPrioByte(ChP,Data)
2956 CHANNEL_T *ChP; Ptr to channel structure
2957 Byte_t Data; The transmit data byte
2958
2959 Return: int: 1 if the bytes is successfully written, otherwise 0.
2960
2961 Comments: The priority byte is transmitted before any data in the Tx FIFO.
2962
2963 Warnings: No context switches are allowed while executing this function.
2964 */
sWriteTxPrioByte(CHANNEL_T * ChP,Byte_t Data)2965 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
2966 {
2967 Byte_t DWBuf[4]; /* buffer for double word writes */
2968 Word_t *WordPtr; /* must be far because Win SS != DS */
2969 register DWordIO_t IndexAddr;
2970
2971 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
2972 IndexAddr = ChP->IndexAddr;
2973 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
2974 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
2975 return (0); /* nothing sent */
2976
2977 WordPtr = (Word_t *) (&DWBuf[0]);
2978 *WordPtr = ChP->TxPrioBuf; /* data byte address */
2979
2980 DWBuf[2] = Data; /* data byte value */
2981 out32(IndexAddr, DWBuf); /* write it out */
2982
2983 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
2984
2985 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
2986 DWBuf[3] = 0; /* priority buffer pointer */
2987 out32(IndexAddr, DWBuf); /* write it out */
2988 } else { /* write it to Tx FIFO */
2989
2990 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
2991 }
2992 return (1); /* 1 byte sent */
2993 }
2994
2995 /***************************************************************************
2996 Function: sEnInterrupts
2997 Purpose: Enable one or more interrupts for a channel
2998 Call: sEnInterrupts(ChP,Flags)
2999 CHANNEL_T *ChP; Ptr to channel structure
3000 Word_t Flags: Interrupt enable flags, can be any combination
3001 of the following flags:
3002 TXINT_EN: Interrupt on Tx FIFO empty
3003 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3004 sSetRxTrigger())
3005 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3006 MCINT_EN: Interrupt on modem input change
3007 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3008 Interrupt Channel Register.
3009 Return: void
3010 Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3011 enabled. If an interrupt enable flag is not set in Flags, that
3012 interrupt will not be changed. Interrupts can be disabled with
3013 function sDisInterrupts().
3014
3015 This function sets the appropriate bit for the channel in the AIOP's
3016 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
3017 this channel's bit to be set in the AIOP's Interrupt Channel Register.
3018
3019 Interrupts must also be globally enabled before channel interrupts
3020 will be passed on to the host. This is done with function
3021 sEnGlobalInt().
3022
3023 In some cases it may be desirable to disable interrupts globally but
3024 enable channel interrupts. This would allow the global interrupt
3025 status register to be used to determine which AIOPs need service.
3026 */
sEnInterrupts(CHANNEL_T * ChP,Word_t Flags)3027 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3028 {
3029 Byte_t Mask; /* Interrupt Mask Register */
3030
3031 ChP->RxControl[2] |=
3032 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3033
3034 out32(ChP->IndexAddr, ChP->RxControl);
3035
3036 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3037
3038 out32(ChP->IndexAddr, ChP->TxControl);
3039
3040 if (Flags & CHANINT_EN) {
3041 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3042 sOutB(ChP->IntMask, Mask);
3043 }
3044 }
3045
3046 /***************************************************************************
3047 Function: sDisInterrupts
3048 Purpose: Disable one or more interrupts for a channel
3049 Call: sDisInterrupts(ChP,Flags)
3050 CHANNEL_T *ChP; Ptr to channel structure
3051 Word_t Flags: Interrupt flags, can be any combination
3052 of the following flags:
3053 TXINT_EN: Interrupt on Tx FIFO empty
3054 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3055 sSetRxTrigger())
3056 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3057 MCINT_EN: Interrupt on modem input change
3058 CHANINT_EN: Disable channel interrupt signal to the
3059 AIOP's Interrupt Channel Register.
3060 Return: void
3061 Comments: If an interrupt flag is set in Flags, that interrupt will be
3062 disabled. If an interrupt flag is not set in Flags, that
3063 interrupt will not be changed. Interrupts can be enabled with
3064 function sEnInterrupts().
3065
3066 This function clears the appropriate bit for the channel in the AIOP's
3067 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3068 this channel's bit from being set in the AIOP's Interrupt Channel
3069 Register.
3070 */
sDisInterrupts(CHANNEL_T * ChP,Word_t Flags)3071 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3072 {
3073 Byte_t Mask; /* Interrupt Mask Register */
3074
3075 ChP->RxControl[2] &=
3076 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3077 out32(ChP->IndexAddr, ChP->RxControl);
3078 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3079 out32(ChP->IndexAddr, ChP->TxControl);
3080
3081 if (Flags & CHANINT_EN) {
3082 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3083 sOutB(ChP->IntMask, Mask);
3084 }
3085 }
3086
sSetInterfaceMode(CHANNEL_T * ChP,Byte_t mode)3087 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3088 {
3089 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3090 }
3091
3092 /*
3093 * Not an official SSCI function, but how to reset RocketModems.
3094 * ISA bus version
3095 */
sModemReset(CONTROLLER_T * CtlP,int chan,int on)3096 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3097 {
3098 ByteIO_t addr;
3099 Byte_t val;
3100
3101 addr = CtlP->AiopIO[0] + 0x400;
3102 val = sInB(CtlP->MReg3IO);
3103 /* if AIOP[1] is not enabled, enable it */
3104 if ((val & 2) == 0) {
3105 val = sInB(CtlP->MReg2IO);
3106 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3107 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3108 }
3109
3110 sEnAiop(CtlP, 1);
3111 if (!on)
3112 addr += 8;
3113 sOutB(addr + chan, 0); /* apply or remove reset */
3114 sDisAiop(CtlP, 1);
3115 }
3116
3117 /*
3118 * Not an official SSCI function, but how to reset RocketModems.
3119 * PCI bus version
3120 */
sPCIModemReset(CONTROLLER_T * CtlP,int chan,int on)3121 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3122 {
3123 ByteIO_t addr;
3124
3125 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3126 if (!on)
3127 addr += 8;
3128 sOutB(addr + chan, 0); /* apply or remove reset */
3129 }
3130
3131 /* Returns the line number given the controller (board), aiop and channel number */
GetLineNumber(int ctrl,int aiop,int ch)3132 static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3133 {
3134 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3135 }
3136
3137 /*
3138 * Stores the line number associated with a given controller (board), aiop
3139 * and channel number.
3140 * Returns: The line number assigned
3141 */
SetLineNumber(int ctrl,int aiop,int ch)3142 static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3143 {
3144 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3145 return (nextLineNumber - 1);
3146 }
3147