1 #ifndef __HPET__ 2 #define __HPET__ 1 3 4 #include <uapi/linux/hpet.h> 5 6 7 /* 8 * Offsets into HPET Registers 9 */ 10 11 struct hpet { 12 u64 hpet_cap; /* capabilities */ 13 u64 res0; /* reserved */ 14 u64 hpet_config; /* configuration */ 15 u64 res1; /* reserved */ 16 u64 hpet_isr; /* interrupt status reg */ 17 u64 res2[25]; /* reserved */ 18 union { /* main counter */ 19 u64 _hpet_mc64; 20 u32 _hpet_mc32; 21 unsigned long _hpet_mc; 22 } _u0; 23 u64 res3; /* reserved */ 24 struct hpet_timer { 25 u64 hpet_config; /* configuration/cap */ 26 union { /* timer compare register */ 27 u64 _hpet_hc64; 28 u32 _hpet_hc32; 29 unsigned long _hpet_compare; 30 } _u1; 31 u64 hpet_fsb[2]; /* FSB route */ 32 } hpet_timers[1]; 33 }; 34 35 #define hpet_mc _u0._hpet_mc 36 #define hpet_compare _u1._hpet_compare 37 38 #define HPET_MAX_TIMERS (32) 39 #define HPET_MAX_IRQ (32) 40 41 /* 42 * HPET general capabilities register 43 */ 44 45 #define HPET_COUNTER_CLK_PERIOD_MASK (0xffffffff00000000ULL) 46 #define HPET_COUNTER_CLK_PERIOD_SHIFT (32UL) 47 #define HPET_VENDOR_ID_MASK (0x00000000ffff0000ULL) 48 #define HPET_VENDOR_ID_SHIFT (16ULL) 49 #define HPET_LEG_RT_CAP_MASK (0x8000) 50 #define HPET_COUNTER_SIZE_MASK (0x2000) 51 #define HPET_NUM_TIM_CAP_MASK (0x1f00) 52 #define HPET_NUM_TIM_CAP_SHIFT (8ULL) 53 54 /* 55 * HPET general configuration register 56 */ 57 58 #define HPET_LEG_RT_CNF_MASK (2UL) 59 #define HPET_ENABLE_CNF_MASK (1UL) 60 61 62 /* 63 * Timer configuration register 64 */ 65 66 #define Tn_INT_ROUTE_CAP_MASK (0xffffffff00000000ULL) 67 #define Tn_INT_ROUTE_CAP_SHIFT (32UL) 68 #define Tn_FSB_INT_DELCAP_MASK (0x8000UL) 69 #define Tn_FSB_INT_DELCAP_SHIFT (15) 70 #define Tn_FSB_EN_CNF_MASK (0x4000UL) 71 #define Tn_FSB_EN_CNF_SHIFT (14) 72 #define Tn_INT_ROUTE_CNF_MASK (0x3e00UL) 73 #define Tn_INT_ROUTE_CNF_SHIFT (9) 74 #define Tn_32MODE_CNF_MASK (0x0100UL) 75 #define Tn_VAL_SET_CNF_MASK (0x0040UL) 76 #define Tn_SIZE_CAP_MASK (0x0020UL) 77 #define Tn_PER_INT_CAP_MASK (0x0010UL) 78 #define Tn_TYPE_CNF_MASK (0x0008UL) 79 #define Tn_INT_ENB_CNF_MASK (0x0004UL) 80 #define Tn_INT_TYPE_CNF_MASK (0x0002UL) 81 82 /* 83 * Timer FSB Interrupt Route Register 84 */ 85 86 #define Tn_FSB_INT_ADDR_MASK (0xffffffff00000000ULL) 87 #define Tn_FSB_INT_ADDR_SHIFT (32UL) 88 #define Tn_FSB_INT_VAL_MASK (0x00000000ffffffffULL) 89 90 /* 91 * exported interfaces 92 */ 93 94 struct hpet_data { 95 unsigned long hd_phys_address; 96 void __iomem *hd_address; 97 unsigned short hd_nirqs; 98 unsigned int hd_state; /* timer allocated */ 99 unsigned int hd_irq[HPET_MAX_TIMERS]; 100 }; 101 hpet_reserve_timer(struct hpet_data * hd,int timer)102static inline void hpet_reserve_timer(struct hpet_data *hd, int timer) 103 { 104 hd->hd_state |= (1 << timer); 105 return; 106 } 107 108 int hpet_alloc(struct hpet_data *); 109 110 #endif /* !__HPET__ */ 111