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1 #ifndef _LINUX_INCLUDE_MFD_IMX25_TSADC_H_
2 #define _LINUX_INCLUDE_MFD_IMX25_TSADC_H_
3 
4 struct regmap;
5 struct clk;
6 
7 struct mx25_tsadc {
8 	struct regmap *regs;
9 	struct irq_domain *domain;
10 	struct clk *clk;
11 };
12 
13 #define MX25_TSC_TGCR			0x00
14 #define MX25_TSC_TGSR			0x04
15 #define MX25_TSC_TICR			0x08
16 
17 /* The same register layout for TC and GC queue */
18 #define MX25_ADCQ_FIFO			0x00
19 #define MX25_ADCQ_CR			0x04
20 #define MX25_ADCQ_SR			0x08
21 #define MX25_ADCQ_MR			0x0c
22 #define MX25_ADCQ_ITEM_7_0		0x20
23 #define MX25_ADCQ_ITEM_15_8		0x24
24 #define MX25_ADCQ_CFG(n)		(0x40 + ((n) * 0x4))
25 
26 #define MX25_ADCQ_MR_MASK		0xffffffff
27 
28 /* TGCR */
29 #define MX25_TGCR_PDBTIME(x)		((x) << 25)
30 #define MX25_TGCR_PDBTIME_MASK		GENMASK(31, 25)
31 #define MX25_TGCR_PDBEN			BIT(24)
32 #define MX25_TGCR_PDEN			BIT(23)
33 #define MX25_TGCR_ADCCLKCFG(x)		((x) << 16)
34 #define MX25_TGCR_GET_ADCCLK(x)		(((x) >> 16) & 0x1f)
35 #define MX25_TGCR_INTREFEN		BIT(10)
36 #define MX25_TGCR_POWERMODE_MASK	GENMASK(9, 8)
37 #define MX25_TGCR_POWERMODE_SAVE	(1 << 8)
38 #define MX25_TGCR_POWERMODE_ON		(2 << 8)
39 #define MX25_TGCR_STLC			BIT(5)
40 #define MX25_TGCR_SLPC			BIT(4)
41 #define MX25_TGCR_FUNC_RST		BIT(2)
42 #define MX25_TGCR_TSC_RST		BIT(1)
43 #define MX25_TGCR_CLK_EN		BIT(0)
44 
45 /* TGSR */
46 #define MX25_TGSR_SLP_INT		BIT(2)
47 #define MX25_TGSR_GCQ_INT		BIT(1)
48 #define MX25_TGSR_TCQ_INT		BIT(0)
49 
50 /* ADCQ_ITEM_* */
51 #define _MX25_ADCQ_ITEM(item, x)	((x) << ((item) * 4))
52 #define MX25_ADCQ_ITEM(item, x)		((item) >= 8 ? \
53 		_MX25_ADCQ_ITEM((item) - 8, (x)) : _MX25_ADCQ_ITEM((item), (x)))
54 
55 /* ADCQ_FIFO (TCQFIFO and GCQFIFO) */
56 #define MX25_ADCQ_FIFO_DATA(x)		(((x) >> 4) & 0xfff)
57 #define MX25_ADCQ_FIFO_ID(x)		((x) & 0xf)
58 
59 /* ADCQ_CR (TCQR and GCQR) */
60 #define MX25_ADCQ_CR_PDCFG_LEVEL	BIT(19)
61 #define MX25_ADCQ_CR_PDMSK		BIT(18)
62 #define MX25_ADCQ_CR_FRST		BIT(17)
63 #define MX25_ADCQ_CR_QRST		BIT(16)
64 #define MX25_ADCQ_CR_RWAIT_MASK		GENMASK(15, 12)
65 #define MX25_ADCQ_CR_RWAIT(x)		((x) << 12)
66 #define MX25_ADCQ_CR_WMRK_MASK		GENMASK(11, 8)
67 #define MX25_ADCQ_CR_WMRK(x)		((x) << 8)
68 #define MX25_ADCQ_CR_LITEMID_MASK	(0xf << 4)
69 #define MX25_ADCQ_CR_LITEMID(x)		((x) << 4)
70 #define MX25_ADCQ_CR_RPT		BIT(3)
71 #define MX25_ADCQ_CR_FQS		BIT(2)
72 #define MX25_ADCQ_CR_QSM_MASK		GENMASK(1, 0)
73 #define MX25_ADCQ_CR_QSM_PD		0x1
74 #define MX25_ADCQ_CR_QSM_FQS		0x2
75 #define MX25_ADCQ_CR_QSM_FQS_PD		0x3
76 
77 /* ADCQ_SR (TCQSR and GCQSR) */
78 #define MX25_ADCQ_SR_FDRY		BIT(15)
79 #define MX25_ADCQ_SR_FULL		BIT(14)
80 #define MX25_ADCQ_SR_EMPT		BIT(13)
81 #define MX25_ADCQ_SR_FDN(x)		(((x) >> 8) & 0x1f)
82 #define MX25_ADCQ_SR_FRR		BIT(6)
83 #define MX25_ADCQ_SR_FUR		BIT(5)
84 #define MX25_ADCQ_SR_FOR		BIT(4)
85 #define MX25_ADCQ_SR_EOQ		BIT(1)
86 #define MX25_ADCQ_SR_PD			BIT(0)
87 
88 /* ADCQ_MR (TCQMR and GCQMR) */
89 #define MX25_ADCQ_MR_FDRY_DMA		BIT(31)
90 #define MX25_ADCQ_MR_FER_DMA		BIT(22)
91 #define MX25_ADCQ_MR_FUR_DMA		BIT(21)
92 #define MX25_ADCQ_MR_FOR_DMA		BIT(20)
93 #define MX25_ADCQ_MR_EOQ_DMA		BIT(17)
94 #define MX25_ADCQ_MR_PD_DMA		BIT(16)
95 #define MX25_ADCQ_MR_FDRY_IRQ		BIT(15)
96 #define MX25_ADCQ_MR_FER_IRQ		BIT(6)
97 #define MX25_ADCQ_MR_FUR_IRQ		BIT(5)
98 #define MX25_ADCQ_MR_FOR_IRQ		BIT(4)
99 #define MX25_ADCQ_MR_EOQ_IRQ		BIT(1)
100 #define MX25_ADCQ_MR_PD_IRQ		BIT(0)
101 
102 /* ADCQ_CFG (TICR, TCC0-7,GCC0-7) */
103 #define MX25_ADCQ_CFG_SETTLING_TIME(x)	((x) << 24)
104 #define MX25_ADCQ_CFG_IGS		(1 << 20)
105 #define MX25_ADCQ_CFG_NOS_MASK		GENMASK(19, 16)
106 #define MX25_ADCQ_CFG_NOS(x)		(((x) - 1) << 16)
107 #define MX25_ADCQ_CFG_WIPER		(1 << 15)
108 #define MX25_ADCQ_CFG_YNLR		(1 << 14)
109 #define MX25_ADCQ_CFG_YPLL_HIGH		(0 << 12)
110 #define MX25_ADCQ_CFG_YPLL_OFF		(1 << 12)
111 #define MX25_ADCQ_CFG_YPLL_LOW		(3 << 12)
112 #define MX25_ADCQ_CFG_XNUR_HIGH		(0 << 10)
113 #define MX25_ADCQ_CFG_XNUR_OFF		(1 << 10)
114 #define MX25_ADCQ_CFG_XNUR_LOW		(3 << 10)
115 #define MX25_ADCQ_CFG_XPUL_HIGH		(0 << 9)
116 #define MX25_ADCQ_CFG_XPUL_OFF		(1 << 9)
117 #define MX25_ADCQ_CFG_REFP(sel)		((sel) << 7)
118 #define MX25_ADCQ_CFG_REFP_YP		MX25_ADCQ_CFG_REFP(0)
119 #define MX25_ADCQ_CFG_REFP_XP		MX25_ADCQ_CFG_REFP(1)
120 #define MX25_ADCQ_CFG_REFP_EXT		MX25_ADCQ_CFG_REFP(2)
121 #define MX25_ADCQ_CFG_REFP_INT		MX25_ADCQ_CFG_REFP(3)
122 #define MX25_ADCQ_CFG_REFP_MASK		GENMASK(8, 7)
123 #define MX25_ADCQ_CFG_IN(sel)		((sel) << 4)
124 #define MX25_ADCQ_CFG_IN_XP		MX25_ADCQ_CFG_IN(0)
125 #define MX25_ADCQ_CFG_IN_YP		MX25_ADCQ_CFG_IN(1)
126 #define MX25_ADCQ_CFG_IN_XN		MX25_ADCQ_CFG_IN(2)
127 #define MX25_ADCQ_CFG_IN_YN		MX25_ADCQ_CFG_IN(3)
128 #define MX25_ADCQ_CFG_IN_WIPER		MX25_ADCQ_CFG_IN(4)
129 #define MX25_ADCQ_CFG_IN_AUX0		MX25_ADCQ_CFG_IN(5)
130 #define MX25_ADCQ_CFG_IN_AUX1		MX25_ADCQ_CFG_IN(6)
131 #define MX25_ADCQ_CFG_IN_AUX2		MX25_ADCQ_CFG_IN(7)
132 #define MX25_ADCQ_CFG_REFN(sel)		((sel) << 2)
133 #define MX25_ADCQ_CFG_REFN_XN		MX25_ADCQ_CFG_REFN(0)
134 #define MX25_ADCQ_CFG_REFN_YN		MX25_ADCQ_CFG_REFN(1)
135 #define MX25_ADCQ_CFG_REFN_NGND		MX25_ADCQ_CFG_REFN(2)
136 #define MX25_ADCQ_CFG_REFN_NGND2	MX25_ADCQ_CFG_REFN(3)
137 #define MX25_ADCQ_CFG_REFN_MASK		GENMASK(3, 2)
138 #define MX25_ADCQ_CFG_PENIACK		(1 << 1)
139 
140 #endif  /* _LINUX_INCLUDE_MFD_IMX25_TSADC_H_ */
141