1 /* 2 * intel_bxtwc.h - Header file for Intel Broxton Whiskey Cove PMIC 3 * 4 * Copyright (C) 2015 Intel Corporation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16 #include <linux/mfd/intel_soc_pmic.h> 17 18 #ifndef __INTEL_BXTWC_H__ 19 #define __INTEL_BXTWC_H__ 20 21 /* BXT WC devices */ 22 #define BXTWC_DEVICE1_ADDR 0x4E 23 #define BXTWC_DEVICE2_ADDR 0x4F 24 #define BXTWC_DEVICE3_ADDR 0x5E 25 26 /* device1 Registers */ 27 #define BXTWC_CHIPID 0x4E00 28 #define BXTWC_CHIPVER 0x4E01 29 30 #define BXTWC_SCHGRIRQ0_ADDR 0x5E1A 31 #define BXTWC_CHGRCTRL0_ADDR 0x5E16 32 #define BXTWC_CHGRCTRL1_ADDR 0x5E17 33 #define BXTWC_CHGRCTRL2_ADDR 0x5E18 34 #define BXTWC_CHGRSTATUS_ADDR 0x5E19 35 #define BXTWC_THRMBATZONE_ADDR 0x4F22 36 37 #define BXTWC_USBPATH_ADDR 0x5E19 38 #define BXTWC_USBPHYCTRL_ADDR 0x5E07 39 #define BXTWC_USBIDCTRL_ADDR 0x5E05 40 #define BXTWC_USBIDEN_MASK 0x01 41 #define BXTWC_USBIDSTAT_ADDR 0x00FF 42 #define BXTWC_USBSRCDETSTATUS_ADDR 0x5E29 43 44 #define BXTWC_DBGUSBBC1_ADDR 0x5FE0 45 #define BXTWC_DBGUSBBC2_ADDR 0x5FE1 46 #define BXTWC_DBGUSBBCSTAT_ADDR 0x5FE2 47 48 #define BXTWC_WAKESRC_ADDR 0x4E22 49 #define BXTWC_WAKESRC2_ADDR 0x4EE5 50 #define BXTWC_CHRTTADDR_ADDR 0x5E22 51 #define BXTWC_CHRTTDATA_ADDR 0x5E23 52 53 #define BXTWC_STHRMIRQ0_ADDR 0x4F19 54 #define WC_MTHRMIRQ1_ADDR 0x4E12 55 #define WC_STHRMIRQ1_ADDR 0x4F1A 56 #define WC_STHRMIRQ2_ADDR 0x4F1B 57 58 #define BXTWC_THRMZN0H_ADDR 0x4F44 59 #define BXTWC_THRMZN0L_ADDR 0x4F45 60 #define BXTWC_THRMZN1H_ADDR 0x4F46 61 #define BXTWC_THRMZN1L_ADDR 0x4F47 62 #define BXTWC_THRMZN2H_ADDR 0x4F48 63 #define BXTWC_THRMZN2L_ADDR 0x4F49 64 #define BXTWC_THRMZN3H_ADDR 0x4F4A 65 #define BXTWC_THRMZN3L_ADDR 0x4F4B 66 #define BXTWC_THRMZN4H_ADDR 0x4F4C 67 #define BXTWC_THRMZN4L_ADDR 0x4F4D 68 69 #endif 70