1 /* 2 * include/linux/spi/spidev.h 3 * 4 * Copyright (C) 2006 SWAPP 5 * Andrea Paterniani <a.paterniani@swapp-eng.it> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22 #ifndef SPIDEV_H 23 #define SPIDEV_H 24 25 #include <linux/types.h> 26 #include <linux/ioctl.h> 27 28 /* User space versions of kernel symbols for SPI clocking modes, 29 * matching <linux/spi/spi.h> 30 */ 31 32 #define SPI_CPHA 0x01 33 #define SPI_CPOL 0x02 34 35 #define SPI_MODE_0 (0|0) 36 #define SPI_MODE_1 (0|SPI_CPHA) 37 #define SPI_MODE_2 (SPI_CPOL|0) 38 #define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) 39 40 #define SPI_CS_HIGH 0x04 41 #define SPI_LSB_FIRST 0x08 42 #define SPI_3WIRE 0x10 43 #define SPI_LOOP 0x20 44 #define SPI_NO_CS 0x40 45 #define SPI_READY 0x80 46 #define SPI_TX_DUAL 0x100 47 #define SPI_TX_QUAD 0x200 48 #define SPI_RX_DUAL 0x400 49 #define SPI_RX_QUAD 0x800 50 51 /*---------------------------------------------------------------------------*/ 52 53 /* IOCTL commands */ 54 55 #define SPI_IOC_MAGIC 'k' 56 57 /** 58 * struct spi_ioc_transfer - describes a single SPI transfer 59 * @tx_buf: Holds pointer to userspace buffer with transmit data, or null. 60 * If no data is provided, zeroes are shifted out. 61 * @rx_buf: Holds pointer to userspace buffer for receive data, or null. 62 * @len: Length of tx and rx buffers, in bytes. 63 * @speed_hz: Temporary override of the device's bitrate. 64 * @bits_per_word: Temporary override of the device's wordsize. 65 * @delay_usecs: If nonzero, how long to delay after the last bit transfer 66 * before optionally deselecting the device before the next transfer. 67 * @cs_change: True to deselect device before starting the next transfer. 68 * 69 * This structure is mapped directly to the kernel spi_transfer structure; 70 * the fields have the same meanings, except of course that the pointers 71 * are in a different address space (and may be of different sizes in some 72 * cases, such as 32-bit i386 userspace over a 64-bit x86_64 kernel). 73 * Zero-initialize the structure, including currently unused fields, to 74 * accommodate potential future updates. 75 * 76 * SPI_IOC_MESSAGE gives userspace the equivalent of kernel spi_sync(). 77 * Pass it an array of related transfers, they'll execute together. 78 * Each transfer may be half duplex (either direction) or full duplex. 79 * 80 * struct spi_ioc_transfer mesg[4]; 81 * ... 82 * status = ioctl(fd, SPI_IOC_MESSAGE(4), mesg); 83 * 84 * So for example one transfer might send a nine bit command (right aligned 85 * in a 16-bit word), the next could read a block of 8-bit data before 86 * terminating that command by temporarily deselecting the chip; the next 87 * could send a different nine bit command (re-selecting the chip), and the 88 * last transfer might write some register values. 89 */ 90 struct spi_ioc_transfer { 91 __u64 tx_buf; 92 __u64 rx_buf; 93 94 __u32 len; 95 __u32 speed_hz; 96 97 __u16 delay_usecs; 98 __u8 bits_per_word; 99 __u8 cs_change; 100 __u8 tx_nbits; 101 __u8 rx_nbits; 102 __u16 pad; 103 104 /* If the contents of 'struct spi_ioc_transfer' ever change 105 * incompatibly, then the ioctl number (currently 0) must change; 106 * ioctls with constant size fields get a bit more in the way of 107 * error checking than ones (like this) where that field varies. 108 * 109 * NOTE: struct layout is the same in 64bit and 32bit userspace. 110 */ 111 }; 112 113 /* not all platforms use <asm-generic/ioctl.h> or _IOC_TYPECHECK() ... */ 114 #define SPI_MSGSIZE(N) \ 115 ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \ 116 ? ((N)*(sizeof (struct spi_ioc_transfer))) : 0) 117 #define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)]) 118 119 120 /* Read / Write of SPI mode (SPI_MODE_0..SPI_MODE_3) (limited to 8 bits) */ 121 #define SPI_IOC_RD_MODE _IOR(SPI_IOC_MAGIC, 1, __u8) 122 #define SPI_IOC_WR_MODE _IOW(SPI_IOC_MAGIC, 1, __u8) 123 124 /* Read / Write SPI bit justification */ 125 #define SPI_IOC_RD_LSB_FIRST _IOR(SPI_IOC_MAGIC, 2, __u8) 126 #define SPI_IOC_WR_LSB_FIRST _IOW(SPI_IOC_MAGIC, 2, __u8) 127 128 /* Read / Write SPI device word length (1..N) */ 129 #define SPI_IOC_RD_BITS_PER_WORD _IOR(SPI_IOC_MAGIC, 3, __u8) 130 #define SPI_IOC_WR_BITS_PER_WORD _IOW(SPI_IOC_MAGIC, 3, __u8) 131 132 /* Read / Write SPI device default max speed hz */ 133 #define SPI_IOC_RD_MAX_SPEED_HZ _IOR(SPI_IOC_MAGIC, 4, __u32) 134 #define SPI_IOC_WR_MAX_SPEED_HZ _IOW(SPI_IOC_MAGIC, 4, __u32) 135 136 /* Read / Write of the SPI mode field */ 137 #define SPI_IOC_RD_MODE32 _IOR(SPI_IOC_MAGIC, 5, __u32) 138 #define SPI_IOC_WR_MODE32 _IOW(SPI_IOC_MAGIC, 5, __u32) 139 140 141 142 #endif /* SPIDEV_H */ 143