Searched +full:0 +full:x0 (Results 1 – 25 of 472) sorted by relevance
12345678910>>...19
| /Documentation/devicetree/bindings/pci/ |
| D | cdns,cdns-pcie-host.txt | 38 bus-range = <0x0 0xff>;
39 linux,pci-domain = <0>;
42 vendor-id = /bits/ 16 <0x17cd>;
43 device-id = /bits/ 16 <0x0200>;
45 reg = <0x0 0xfb000000 0x0 0x01000000>,
46 <0x0 0x41000000 0x0 0x00001000>,
47 <0x0 0x40000000 0x0 0x04000000>;
50 ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
51 <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
53 #interrupt-cells = <0x1>;
[all …]
|
| D | xgene-pci-msi.txt | 8 - reg: physical base address (0x79000000) and length (0x900000) for controller
13 interrupt number 0x10 to 0x1f.
27 reg = <0x00 0x79000000 0x0 0x900000>;
28 interrupts = <0x0 0x10 0x4>
29 <0x0 0x11 0x4>
30 <0x0 0x12 0x4>
31 <0x0 0x13 0x4>
32 <0x0 0x14 0x4>
33 <0x0 0x15 0x4>
34 <0x0 0x16 0x4>
[all …]
|
| D | 83xx-512x-pci.txt | 12 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
14 /* IDSEL 0x0E -mini PCI */
15 0x7000 0x0 0x0 0x1 &ipic 18 0x8
16 0x7000 0x0 0x0 0x2 &ipic 18 0x8
17 0x7000 0x0 0x0 0x3 &ipic 18 0x8
18 0x7000 0x0 0x0 0x4 &ipic 18 0x8
20 /* IDSEL 0x0F - PCI slot */
21 0x7800 0x0 0x0 0x1 &ipic 17 0x8
22 0x7800 0x0 0x0 0x2 &ipic 18 0x8
23 0x7800 0x0 0x0 0x3 &ipic 17 0x8
[all …]
|
| D | xgene-pci.txt | 35 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
36 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
38 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
39 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
40 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
41 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
42 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
43 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
44 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
45 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
[all …]
|
| D | designware-pcie-ecam.txt | 29 reg = <0x0 0x7f000000 0x0 0xf00000>;
30 bus-range = <0x0 0xe>;
33 ranges = <0x1000000 0x00 0x00010000 0x00 0x7ff00000 0x0 0x00010000>,
34 <0x2000000 0x00 0x70000000 0x00 0x70000000 0x0 0x0f000000>,
35 <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>;
37 #interrupt-cells = <0x1>;
38 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
39 interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 0x0 182 0x4>;
40 msi-map = <0x0 &its 0x0 0x10000>;
|
| D | host-generic-pci.txt | 30 If absent, defaults to <0 255> (i.e. all buses).
39 "bus-range" is specified, this will be bus 0 (the default).
45 If '0', then Linux will assign devices in its usual manner,
81 bus-range = <0x0 0x1>;
84 reg = <0x0 0x40000000 0x0 0x1000000>;
87 ranges = <0x01000000 0x0 0x01000000 0x0 0x01000000 0x0 0x00010000>,
88 <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x3f000000>;
91 #interrupt-cells = <0x1>;
94 interrupt-map = < 0x0 0x0 0x0 0x1 &gic 0x0 0x4 0x1
95 0x800 0x0 0x0 0x1 &gic 0x0 0x5 0x1
[all …]
|
| D | xilinx-nwl-pcie.txt | 34 address. The value must be 0.
48 interrupts = <0 114 4>, <0 115 4>, <0 116 4>, <0 117 4>, <0 118 4>;
50 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
51 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
52 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
53 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
54 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
57 reg = <0x0 0xfd0e0000 0x0 0x1000>,
58 <0x0 0xfd480000 0x0 0x1000>,
59 <0x80 0x00000000 0x0 0x1000000>;
[all …]
|
| D | kirin-pcie.txt | 27 reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>,
28 <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>;
30 bus-range = <0x0 0x1>;
34 ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>;
37 interrupt-map-mask = <0xf800 0 0 7>;
38 interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>,
39 <0x0 0 0 2 &gic 0 0 0 283 4>,
40 <0x0 0 0 3 &gic 0 0 0 284 4>,
41 <0x0 0 0 4 &gic 0 0 0 285 4>;
49 reset-gpios = <&gpio11 1 0 >;
|
| D | pcie-al.txt | 33 reg = <0x0 0xfb600000 0x0 0x00100000
34 0x0 0xfd800000 0x0 0x00010000
35 0x0 0xfd810000 0x0 0x00001000>;
37 bus-range = <0 255>;
43 interrupt-map-mask = <0x00 0 0 7>;
44 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; /* INTa */
45 ranges = <0x02000000 0x0 0xc0010000 0x0 0xc0010000 0x0 0x07ff0000>;
|
| D | amlogic,meson-pcie.txt | 40 reg = <0x0 0xf9800000 0x0 0x400000
41 0x0 0xff646000 0x0 0x2000
42 0x0 0xff644000 0x0 0x2000
43 0x0 0xf9f00000 0x0 0x100000>;
48 interrupt-map-mask = <0 0 0 0>;
49 interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
50 bus-range = <0x0 0xff>;
54 ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>;
|
| /Documentation/devicetree/bindings/ata/ |
| D | apm-xgene.txt | 41 reg = <0x0 0x1f22a000 0x0 0x100>;
47 reg = <0x0 0x1f23a000 0x0 0x100>;
53 reg = <0x0 0x1a400000 0x0 0x1000>,
54 <0x0 0x1f220000 0x0 0x1000>,
55 <0x0 0x1f22d000 0x0 0x1000>,
56 <0x0 0x1f22e000 0x0 0x1000>,
57 <0x0 0x1f227000 0x0 0x1000>;
58 interrupts = <0x0 0x87 0x4>;
60 clocks = <&sataclk 0>;
61 phys = <&phy2 0>;
[all …]
|
| /Documentation/devicetree/bindings/dma/ |
| D | apm-xgene-dma.txt | 27 clocks = <&socplldiv2 0>;
28 reg = <0x0 0x1f27c000 0x0 0x1000>;
36 reg = <0x0 0x1f270000 0x0 0x10000>,
37 <0x0 0x1f200000 0x0 0x10000>,
38 <0x0 0x1b000000 0x0 0x400000>,
39 <0x0 0x1054a000 0x0 0x100>;
40 interrupts = <0x0 0x82 0x4>,
41 <0x0 0xb8 0x4>,
42 <0x0 0xb9 0x4>,
43 <0x0 0xba 0x4>,
[all …]
|
| /Documentation/devicetree/bindings/perf/ |
| D | apm-xgene-pmu.txt | 43 reg = <0x0 0x7e200000 0x0 0x1000>;
48 reg = <0x0 0x7e700000 0x0 0x1000>;
53 reg = <0x0 0x7e720000 0x0 0x1000>;
64 reg = <0x0 0x78810000 0x0 0x1000>;
65 interrupts = <0x0 0x22 0x4>;
69 reg = <0x0 0x7e610000 0x0 0x1000>;
74 reg = <0x0 0x7e940000 0x0 0x1000>;
79 reg = <0x0 0x7e710000 0x0 0x1000>;
80 enable-bit-index = <0>;
85 reg = <0x0 0x7e730000 0x0 0x1000>;
[all …]
|
| /Documentation/devicetree/bindings/crypto/ |
| D | hisilicon,hip07-sec.txt | 9 Region 0 has registers to control the backend processing engines.
16 Interrupt 0 is for the SEC unit error queue.
29 reg = <0x400 0xd0000000 0x0 0x10000
30 0x400 0xd2000000 0x0 0x10000
31 0x400 0xd2010000 0x0 0x10000
32 0x400 0xd2020000 0x0 0x10000
33 0x400 0xd2030000 0x0 0x10000
34 0x400 0xd2040000 0x0 0x10000
35 0x400 0xd2050000 0x0 0x10000
36 0x400 0xd2060000 0x0 0x10000
[all …]
|
| /Documentation/devicetree/bindings/edac/ |
| D | apm-xgene-edac.txt | 53 reg = <0x0 0x7e200000 0x0 0x1000>;
58 reg = <0x0 0x7e700000 0x0 0x1000>;
63 reg = <0x0 0x7e720000 0x0 0x1000>;
68 reg = <0x0 0x1054a000 0x0 0x20>;
73 reg = <0x0 0x7e000000 0x0 0x10>;
86 reg = <0x0 0x78800000 0x0 0x100>;
87 interrupts = <0x0 0x20 0x4>,
88 <0x0 0x21 0x4>,
89 <0x0 0x27 0x4>;
93 reg = <0x0 0x7e800000 0x0 0x1000>;
[all …]
|
| /Documentation/devicetree/bindings/mailbox/ |
| D | xgene-slimpro-mailbox.txt | 14 - interrupts: 8 interrupts must be from 0 to 7, interrupt 0 define the
15 the interrupt for mailbox channel 0 and interrupt 1 for
25 reg = <0x0 0x10540000 0x0 0xa000>;
27 interrupts = <0x0 0x0 0x4>,
28 <0x0 0x1 0x4>,
29 <0x0 0x2 0x4>,
30 <0x0 0x3 0x4>,
31 <0x0 0x4 0x4>,
32 <0x0 0x5 0x4>,
33 <0x0 0x6 0x4>,
[all …]
|
| /Documentation/devicetree/bindings/memory-controllers/fsl/ |
| D | ifc.txt | 37 reg = <0x0 0xffe1e000 0 0x2000>;
42 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
43 0x1 0x0 0x0 0xffa00000 0x00010000
44 0x3 0x0 0x0 0xffb00000 0x00020000>;
46 flash@0,0 {
50 reg = <0x0 0x0 0x2000000>;
54 partition@0 {
56 reg = <0x0 0x02000000>;
61 flash@1,0 {
65 reg = <0x1 0x0 0x10000>;
[all …]
|
| /Documentation/devicetree/bindings/rtc/ |
| D | rtc-fsl-ftm-alarm.txt | 27 reg = <0x0 0x1e34040 0x0 0x18>;
33 reg = <0x0 0x2800000 0x0 0x10000>;
34 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
35 interrupts = <0 44 4>;
|
| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | lbc.txt | 19 reg = <0xf0010100 0x40>;
21 ranges = <0x0 0x0 0xfe000000 0x02000000
22 0x1 0x0 0xf4500000 0x00008000
23 0x2 0x0 0xfd810000 0x00010000>;
25 flash@0,0 {
27 reg = <0x0 0x0 0x2000000>;
32 board-control@1,0 {
33 reg = <0x1 0x0 0x20>;
37 simple-periph@2,0 {
39 reg = <0x2 0x0 0x10000>;
[all …]
|
| /Documentation/devicetree/bindings/clock/ |
| D | xgene.txt | 50 Default is 0.
51 - csr-mask : CSR reset mask bit. Default is 0xF.
53 Default is 0x8.
54 - enable-mask : CSR enable mask bit. Default is 0xF.
56 Default is 0x0.
57 - divider-width : Width of the divider register. Default is 0.
58 - divider-shift : Bit shift of the divider register. Default is 0.
65 clocks = <&refclk 0>;
67 reg = <0x0 0x17000100 0x0 0x1000>;
69 type = <0>;
[all …]
|
| /Documentation/devicetree/bindings/mtd/ |
| D | ti,am654-hbmc.txt | 23 reg = <0x0 0x47000000 0x0 0x100>;
31 mux-reg-masks = <0x4 0x2>; /* 0: reg 0x4, bit 1 */
37 reg = <0x0 0x47034000 0x0 0x100>,
38 <0x5 0x00000000 0x1 0x0000000>;
42 ranges = <0x0 0x0 0x5 0x00000000 0x4000000>, /* CS0 - 64MB */
43 <0x1 0x0 0x5 0x04000000 0x4000000>; /* CS1 - 64MB */
44 mux-controls = <&hbmc_mux 0>;
47 flash@0,0 {
49 reg = <0x0 0x0 0x4000000>;
|
| /Documentation/devicetree/bindings/gpu/ |
| D | nvidia,gk20a.txt | 42 reg = <0x0 0x57000000 0x0 0x01000000>,
43 <0x0 0x58000000 0x0 0x01000000>;
60 reg = <0x0 0x57000000 0x0 0x01000000>,
61 <0x0 0x58000000 0x0 0x01000000>;
78 reg = <0x0 0x17000000 0x0 0x1000000>,
79 <0x0 0x18000000 0x0 0x1000000>;
|
| /Documentation/devicetree/bindings/spi/ |
| D | brcm,spi-bcm-qspi.txt | 22 Must be <0>, also as required by generic SPI binding.
77 #address-cells = <0x1>;
78 #size-cells = <0x0>;
80 reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>;
82 interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>;
83 interrupt-parent = <0x1c>;
95 m25p80@0 {
96 #size-cells = <0x2>;
97 #address-cells = <0x2>;
99 reg = <0x0>;
[all …]
|
| /Documentation/devicetree/bindings/net/ |
| D | brcm,bcmgenet.txt | 46 - #size-cells: size of the cells for MDIO bus addressing, should be 0
60 #address-cells = <0x1>;
61 #size-cells = <0x1>;
62 reg = <0xf0b60000 0xfc4c>;
63 interrupts = <0x0 0x14 0x0>, <0x0 0x15 0x0>;
67 #address-cells = <0x1>;
68 #size-cells = <0x0>;
69 reg = <0xe14 0x8>;
73 reg = <0x1>;
83 fixed-link = <1 0 1000 0 0>;
[all …]
|
| /Documentation/devicetree/bindings/usb/ |
| D | ux500-usb.txt | 19 reg = <0xa03e0000 0x10000>;
20 interrupts = <0 23 0x4>;
25 dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
26 <&dma 38 0 0x0>, /* Logical - MemToDev */
27 <&dma 37 0 0x2>, /* Logical - DevToMem */
28 <&dma 37 0 0x0>, /* Logical - MemToDev */
29 <&dma 36 0 0x2>, /* Logical - DevToMem */
30 <&dma 36 0 0x0>, /* Logical - MemToDev */
31 <&dma 19 0 0x2>, /* Logical - DevToMem */
32 <&dma 19 0 0x0>, /* Logical - MemToDev */
[all …]
|
12345678910>>...19