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1Amlogic Meson AXG DWC PCIE SoC controller
2
3Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
4It shares common functions with the PCIe DesignWare core driver and
5inherits common properties defined in
6Documentation/devicetree/bindings/pci/designware-pcie.txt.
7
8Additional properties are described here:
9
10Required properties:
11- compatible:
12	should contain "amlogic,axg-pcie" to identify the core.
13- reg:
14	should contain the configuration address space.
15- reg-names: Must be
16	- "elbi"	External local bus interface registers
17	- "cfg"		Meson specific registers
18	- "phy"		Meson PCIE PHY registers
19	- "config"	PCIe configuration space
20- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
21- clocks: Must contain an entry for each entry in clock-names.
22- clock-names: Must include the following entries:
23	- "pclk"       PCIe GEN 100M PLL clock
24	- "port"       PCIe_x(A or B) RC clock gate
25	- "general"    PCIe Phy clock
26	- "mipi"       PCIe_x(A or B) 100M ref clock gate
27- resets: phandle to the reset lines.
28- reset-names: must contain "phy" "port" and "apb"
29       - "phy"         Share PHY reset
30       - "port"        Port A or B reset
31       - "apb"         Share APB reset
32- device_type:
33	should be "pci". As specified in designware-pcie.txt
34
35
36Example configuration:
37
38	pcie: pcie@f9800000 {
39			compatible = "amlogic,axg-pcie", "snps,dw-pcie";
40			reg = <0x0 0xf9800000 0x0 0x400000
41					0x0 0xff646000 0x0 0x2000
42					0x0 0xff644000 0x0 0x2000
43					0x0 0xf9f00000 0x0 0x100000>;
44			reg-names = "elbi", "cfg", "phy", "config";
45			reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
46			interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
47			#interrupt-cells = <1>;
48			interrupt-map-mask = <0 0 0 0>;
49			interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
50			bus-range = <0x0 0xff>;
51			#address-cells = <3>;
52			#size-cells = <2>;
53			device_type = "pci";
54			ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>;
55
56			clocks = <&clkc CLKID_USB
57					&clkc CLKID_MIPI_ENABLE
58					&clkc CLKID_PCIE_A
59					&clkc CLKID_PCIE_CML_EN0>;
60			clock-names = "general",
61					"mipi",
62					"pclk",
63					"port";
64			resets = <&reset RESET_PCIE_PHY>,
65				<&reset RESET_PCIE_A>,
66				<&reset RESET_PCIE_APB>;
67			reset-names = "phy",
68					"port",
69					"apb";
70	};
71