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| /Documentation/devicetree/bindings/soc/fsl/ |
| D | guts.txt | 1 * Global Utilities Block
3 The global utilities block controls power management, I/O device
11 global-utilities.
21 - fsl,has-rstcr : Indicates that the global utilities register set
28 - little-endian : Indicates that the global utilities block is little
32 global-utilities@e0000 { /* global utilities block */
38 guts: global-utilities@e0000 {
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| /Documentation/devicetree/bindings/mailbox/ |
| D | qcom,apcs-kpss-global.txt | 1 Binding for the Qualcomm APCS global block
4 This binding describes the APCS "global" block found in various Qualcomm
11 "qcom,msm8916-apcs-kpss-global",
12 "qcom,msm8996-apcs-hmss-global"
13 "qcom,msm8998-apcs-hmss-global"
14 "qcom,qcs404-apcs-apps-global"
18 "qcom,ipq8074-apcs-apps-global"
23 Definition: must specify the base address and size of the global block
45 compatible = "qcom,msm8996-apcs-hmss-global";
65 compatible = "qcom,msm8916-apcs-kpss-global";
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| /Documentation/devicetree/bindings/arm/marvell/ |
| D | marvell,dove.txt | 9 * Global Configuration registers
11 Global Configuration registers of Dove SoC are shared by a syscon node.
14 - compatible: must contain "marvell,dove-global-config" and "syscon".
15 - reg: base address and size of the Global Configuration registers.
19 gconf: global-config@e802c {
20 compatible = "marvell,dove-global-config", "syscon";
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| /Documentation/devicetree/bindings/timer/ |
| D | arm,global_timer.yaml | 7 title: ARM Global Timer
13 Cortex-A9 are often associated with a per-core Global timer.
19 - arm,cortex-a5-global-timer
20 - arm,cortex-a9-global-timer
41 compatible = "arm,cortex-a9-global-timer";
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| D | samsung,exynos4210-mct.txt | 4 global timer and CPU local timers. The global timer is a 64-bit free running
21 should be specified after the four global timer interrupts have been
24 0: Global Timer Interrupt 0
25 1: Global Timer Interrupt 1
26 2: Global Timer Interrupt 2
27 3: Global Timer Interrupt 3
41 in addition to four global timer interrupts.
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| D | marvell,armada-370-xp-timer.txt | 9 - interrupts: Should contain the list of Global Timer interrupts and
12 pair for the Global Timer registers, second pair for the
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| /Documentation/devicetree/bindings/arm/socionext/ |
| D | uniphier.txt | 30 - Global Board: "socionext,uniphier-ld11-global"
34 - Global Board: "socionext,uniphier-ld20-global"
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| /Documentation/devicetree/bindings/reset/ |
| D | qcom,pdc-global.txt | 1 PDC Global
4 This binding describes a reset-controller found on PDC-Global (Power Domain
12 "qcom,sdm845-pdc-global"
28 compatible = "qcom,sdm845-pdc-global";
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | sprd,pinctrl.txt | 5 The first block comprises some global control registers, and each
7 to configure for some global common configuration, such as domain
18 global configuration in future. Then we add one "sprd,control" to
19 set these various global control configuration, and we need use
23 bits in one global control register as one pin, thus we should
80 - sprd,control: Control values referring to databook for global control pins.
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| /Documentation/virtual/ |
| D | guest-halt-polling.txt | 18 The basic logic as follows: A global value, guest_halt_poll_ns,
39 wakeup event occurs after the global guest_halt_poll_ns.
46 but before global guest_halt_poll_ns.
65 high once achieves global guest_halt_poll_ns value).
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | ti,sci-inta.txt | 26 Configuration of these Intmap registers that maps global events to vint is done
29 of global events and vints assigned to the requesting host. Management
31 system controller to map specific global event to vint, bit pair.
50 - ti,sci-rm-range-global-event: Array of TISCI subtype ids representing the
51 global events range reaching this IA and are assigned
65 ti,sci-rm-range-global-event = <0x1>;
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpic-timer.txt | 4 - compatible: "fsl,mpic-global-timer"
21 compatible = "fsl,mpic-global-timer";
32 compatible = "fsl,mpic-global-timer";
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| /Documentation/vm/ |
| D | hugetlbfs_reserv.rst | 36 This is a global (per-hstate) count of reserved huge pages. Reserved
157 the global reservation count resv_huge_pages is adjusted something like the
163 Note that the global lock hugetlb_lock is held when checking and adjusting
166 If there were enough free huge pages and the global count resv_huge_pages
173 If hugetlb_reserve_pages() was successful, the global reservation count and
216 exist and the page must be taken from the global free pool if possible.
227 resv_huge_pages--; /* Decrement the global reservation count */
255 a race is detected, the subpool and global reserve counts are adjusted to
269 to the global reservation count (resv_huge_pages).
280 on an error path where a global reserve count must be restored.
[all …]
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | keystone-navigator-dma.txt | 33 configuration.. Navigator cloud global address needs to be programmed
45 - Global control register region (global).
79 reg-names = "global", "txchan", "rxchan",
89 reg-names = "global", "txchan", "rxchan",
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| /Documentation/ABI/testing/ |
| D | sysfs-kernel-mm-swap | 13 VMA, and the global swap readahead algorithm will be
15 false, the global swap readahead algorithm will be
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| D | sysfs-class-ocxl | 28 Size of the global mmio area, as defined in the
35 Give access the global mmio area for the AFU
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| /Documentation/virt/kvm/ |
| D | halt-polling.txt | 48 the global max polling interval (see module params below), or the total block
49 time was greater than the global max polling interval.
52 the global max polling interval then the polling interval can be increased in
59 In the event that the total block time was greater than the global max polling
60 interval then the host will never poll for long enough (limited by the global
78 The kvm module has 3 tuneable module parameters to adjust the global max
86 halt_poll_ns | The global max polling | KVM_HALT_POLL_NS_DEFAULT
124 the period is shorter than the global max polling interval (halt_poll_ns) then
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| /Documentation/devicetree/bindings/iommu/ |
| D | arm,smmu.txt | 36 - #global-interrupts : The number of global interrupts exposed by the
39 - interrupts : Interrupt list, with the first #global-irqs entries
40 corresponding to the global interrupts and any
116 #global-interrupts = <2>;
172 #global-interrupts = <1>;
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| /Documentation/powerpc/ |
| D | dscr.rst | 37 NOTE: Please note here that the system wide global DSCR value never
42 - Global DSCR default: /sys/devices/system/cpu/dscr_default
45 Changing the global DSCR default in the sysfs will change all the CPU
52 the same thing as above but unlike the global one above, it just changes
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| /Documentation/devicetree/bindings/phy/ |
| D | phy-stih407-usb.txt | 11 - reset-names : list of reset signal names. Should be "global" and "port"
23 reset-names = "global", "port";
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| /Documentation/arm/ |
| D | swp_emulation.rst | 24 transaction monitoring block called a global monitor to maintain update
25 atomicity. If your system does not implement a global monitor, this option can
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| /Documentation/livepatch/ |
| D | callbacks.rst | 10 - Safe updates to global data
109 Global data update
112 A pre-patch callback can be useful to update a global variable. For
114 changes a global sysctl, as well as patches the tcp_send_challenge_ack()
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| D | shadow-vars.rst | 11 The implementation introduces a global, in-kernel hashtable that
62 - add <obj, id> to the global hashtable
75 - add <obj, id> pair to the global hashtable
78 - find and remove a <obj, id> reference from global hashtable
86 - find and remove any <*, id> references from global hashtable
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| /Documentation/x86/ |
| D | tlb.rst | 25 be no collateral damage caused by doing the global flush, and
33 cache on modern CPUs, and the global flushes have become more
48 This will cause us to do the global flush for more cases.
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | mediatek,smi-common.txt | 36 - "gals0": the path0 clock of GALS(Global Async Local Sync).
37 - "gals1": the path1 clock of GALS(Global Async Local Sync).
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