1* ARM System MMU Architecture Implementation 2 3ARM SoCs may contain an implementation of the ARM System Memory 4Management Unit Architecture, which can be used to provide 1 or 2 stages 5of address translation to bus masters external to the CPU. 6 7The SMMU may also raise interrupts in response to various fault 8conditions. 9 10** System MMU required properties: 11 12- compatible : Should be one of: 13 14 "arm,smmu-v1" 15 "arm,smmu-v2" 16 "arm,mmu-400" 17 "arm,mmu-401" 18 "arm,mmu-500" 19 "cavium,smmu-v2" 20 "qcom,smmu-v2" 21 22 depending on the particular implementation and/or the 23 version of the architecture implemented. 24 25 Qcom SoCs must contain, as below, SoC-specific compatibles 26 along with "qcom,smmu-v2": 27 "qcom,msm8996-smmu-v2", "qcom,smmu-v2", 28 "qcom,sdm845-smmu-v2", "qcom,smmu-v2". 29 30 Qcom SoCs implementing "arm,mmu-500" must also include, 31 as below, SoC-specific compatibles: 32 "qcom,sdm845-smmu-500", "arm,mmu-500" 33 34- reg : Base address and size of the SMMU. 35 36- #global-interrupts : The number of global interrupts exposed by the 37 device. 38 39- interrupts : Interrupt list, with the first #global-irqs entries 40 corresponding to the global interrupts and any 41 following entries corresponding to context interrupts, 42 specified in order of their indexing by the SMMU. 43 44 For SMMUv2 implementations, there must be exactly one 45 interrupt per context bank. In the case of a single, 46 combined interrupt, it must be listed multiple times. 47 48- #iommu-cells : See Documentation/devicetree/bindings/iommu/iommu.txt 49 for details. With a value of 1, each IOMMU specifier 50 represents a distinct stream ID emitted by that device 51 into the relevant SMMU. 52 53 SMMUs with stream matching support and complex masters 54 may use a value of 2, where the second cell of the 55 IOMMU specifier represents an SMR mask to combine with 56 the ID in the first cell. Care must be taken to ensure 57 the set of matched IDs does not result in conflicts. 58 59** System MMU optional properties: 60 61- dma-coherent : Present if page table walks made by the SMMU are 62 cache coherent with the CPU. 63 64 NOTE: this only applies to the SMMU itself, not 65 masters connected upstream of the SMMU. 66 67- calxeda,smmu-secure-config-access : Enable proper handling of buggy 68 implementations that always use secure access to 69 SMMU configuration registers. In this case non-secure 70 aliases of secure registers have to be used during 71 SMMU configuration. 72 73- stream-match-mask : For SMMUs supporting stream matching and using 74 #iommu-cells = <1>, specifies a mask of bits to ignore 75 when matching stream IDs (e.g. this may be programmed 76 into the SMRn.MASK field of every stream match register 77 used). For cases where it is desirable to ignore some 78 portion of every Stream ID (e.g. for certain MMU-500 79 configurations given globally unique input IDs). This 80 property is not valid for SMMUs using stream indexing, 81 or using stream matching with #iommu-cells = <2>, and 82 may be ignored if present in such cases. 83 84- clock-names: List of the names of clocks input to the device. The 85 required list depends on particular implementation and 86 is as follows: 87 - for "qcom,smmu-v2": 88 - "bus": clock required for downstream bus access and 89 for the smmu ptw, 90 - "iface": clock required to access smmu's registers 91 through the TCU's programming interface. 92 - unspecified for other implementations. 93 94- clocks: Specifiers for all clocks listed in the clock-names property, 95 as per generic clock bindings. 96 97- power-domains: Specifiers for power domains required to be powered on for 98 the SMMU to operate, as per generic power domain bindings. 99 100** Deprecated properties: 101 102- mmu-masters (deprecated in favour of the generic "iommus" binding) : 103 A list of phandles to device nodes representing bus 104 masters for which the SMMU can provide a translation 105 and their corresponding Stream IDs. Each device node 106 linked from this list must have a "#stream-id-cells" 107 property, indicating the number of Stream ID 108 arguments associated with its phandle. 109 110** Examples: 111 112 /* SMMU with stream matching or stream indexing */ 113 smmu1: iommu { 114 compatible = "arm,smmu-v1"; 115 reg = <0xba5e0000 0x10000>; 116 #global-interrupts = <2>; 117 interrupts = <0 32 4>, 118 <0 33 4>, 119 <0 34 4>, /* This is the first context interrupt */ 120 <0 35 4>, 121 <0 36 4>, 122 <0 37 4>; 123 #iommu-cells = <1>; 124 }; 125 126 /* device with two stream IDs, 0 and 7 */ 127 master1 { 128 iommus = <&smmu1 0>, 129 <&smmu1 7>; 130 }; 131 132 133 /* SMMU with stream matching */ 134 smmu2: iommu { 135 ... 136 #iommu-cells = <2>; 137 }; 138 139 /* device with stream IDs 0 and 7 */ 140 master2 { 141 iommus = <&smmu2 0 0>, 142 <&smmu2 7 0>; 143 }; 144 145 /* device with stream IDs 1, 17, 33 and 49 */ 146 master3 { 147 iommus = <&smmu2 1 0x30>; 148 }; 149 150 151 /* ARM MMU-500 with 10-bit stream ID input configuration */ 152 smmu3: iommu { 153 compatible = "arm,mmu-500", "arm,smmu-v2"; 154 ... 155 #iommu-cells = <1>; 156 /* always ignore appended 5-bit TBU number */ 157 stream-match-mask = 0x7c00; 158 }; 159 160 bus { 161 /* bus whose child devices emit one unique 10-bit stream 162 ID each, but may master through multiple SMMU TBUs */ 163 iommu-map = <0 &smmu3 0 0x400>; 164 ... 165 }; 166 167 /* Qcom's arm,smmu-v2 implementation */ 168 smmu4: iommu@d00000 { 169 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 170 reg = <0xd00000 0x10000>; 171 172 #global-interrupts = <1>; 173 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 176 #iommu-cells = <1>; 177 power-domains = <&mmcc MDSS_GDSC>; 178 179 clocks = <&mmcc SMMU_MDP_AXI_CLK>, 180 <&mmcc SMMU_MDP_AHB_CLK>; 181 clock-names = "bus", "iface"; 182 }; 183