Searched full:mmu (Results 1 – 25 of 62) sorted by relevance
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| /Documentation/devicetree/bindings/iommu/ |
| D | samsung,sysmmu.txt | 1 Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
7 System MMU is an IOMMU and supports identical translation table format to
9 permissions, shareability and security protection. In addition, System MMU has
15 master), but one System MMU can handle transactions from only one peripheral
16 device. The relation between a System MMU and the peripheral device needs to be
21 * MFC has one System MMU on its left and right bus.
22 * FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU
24 * M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and
25 the other System MMU on the write channel.
27 For information on assigning System MMU controller to its peripheral devices,
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| D | ti,omap-iommu.txt | 22 back a bus error response on MMU faults.
25 register for enabling the MMU, and the MMU instance
32 /* OMAP3 ISP MMU */
33 mmu_isp: mmu@480bd400 {
43 mmu0_dsp2: mmu@41501000 {
52 mmu1_dsp2: mmu@41502000 {
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| D | arm,smmu.txt | 1 * ARM System MMU Architecture Implementation
10 ** System MMU required properties:
16 "arm,mmu-400"
17 "arm,mmu-401"
18 "arm,mmu-500"
30 Qcom SoCs implementing "arm,mmu-500" must also include,
32 "qcom,sdm845-smmu-500", "arm,mmu-500"
59 ** System MMU optional properties:
78 portion of every Stream ID (e.g. for certain MMU-500
102 - mmu-masters (deprecated in favour of the generic "iommus" binding) :
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| D | rockchip,iommu.txt | 24 - rockchip,disable-mmu-reset : Don't use the mmu reset operation.
25 Some mmu instances may produce unexpected results
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| D | renesas,ipmmu-vmsa.txt | 34 - interrupts: Specifiers for the MMU fault interrupts. For instances that
60 ipmmu_mx: mmu@fe951000 {
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| /Documentation/ |
| D | nommu-mmap.txt | 2 No-MMU memory mapping support
5 The kernel has limited support for memory mapping under no-MMU conditions, such
16 The behaviour is similar between the MMU and no-MMU cases, but not identical;
21 In the MMU case: VM regions backed by arbitrary pages; copy-on-write
24 In the no-MMU case: VM regions backed by arbitrary contiguous runs of
30 shared across fork() or clone() without CLONE_VM in the MMU case. Since
31 the no-MMU case doesn't support these, behaviour is identical to
36 In the MMU case: VM regions backed by pages read from file; changes to
39 In the no-MMU case:
56 are visible in other processes (no MMU protection), but should not
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| /Documentation/virt/kvm/ |
| D | mmu.txt | 1 The x86 kvm shadow mmu
4 The mmu (in arch/x86/kvm, files mmu.[ch] and paging_tmpl.h) is responsible
5 for presenting a standard x86 mmu to the guest, while translating guest
8 The mmu code attempts to satisfy the following requirements:
11 on an emulated mmu except for timing (we attempt to comply
16 - performance: minimize the performance penalty imposed by the mmu
48 The mmu supports first-generation mmu hardware, which allows an atomic switch
51 it exposes is the traditional 2/3/4 level x86 mmu, with support for global
58 The primary job of the mmu is to program the processor's mmu to translate
72 number of required translations matches the hardware, the mmu operates in
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| D | locking.txt | 27 the mmu-lock on x86. Currently, the page fault can be fast in one of the
41 - SPTE_MMU_WRITEABLE means the gfn is writable on mmu. The bit is set when
42 the gfn is writable on guest mmu and it is not write-protected by shadow
134 if it can be updated out of mmu-lock, see spte_has_volatile_bits(), it means,
142 As mentioned before, the spte can be updated to writable out of mmu-lock on
147 Since the spte is "volatile" if it can be updated out of mmu-lock, we always
154 bits. In this case, when the KVM MMU notifier is called to track accesses to a
192 Comment: it is a spinlock since it is used in mmu notifier.
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| /Documentation/xtensa/ |
| D | booting.rst | 9 passed to the kernel in the register a2. The address type depends on MMU type:
11 - For configurations without MMU, with region protection or with MPU the
13 - For configurations with region translarion MMU or with MMUv3 and CONFIG_MMU=n
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| D | index.rst | 12 mmu
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| /Documentation/devicetree/bindings/nios2/ |
| D | nios2.txt | 27 - altr,has-mmu: Specifies CPU support MMU support, should be 1.
61 altr,has-mmu = <1>;
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| /Documentation/devicetree/bindings/gpu/ |
| D | arm,mali-bifrost.yaml | 28 - description: MMU interrupt
34 - const: mmu
76 interrupt-names = "job", "mmu", "gpu";
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| D | arm,mali-midgard.yaml | 53 - description: MMU interrupt
59 - const: mmu
127 interrupt-names = "job", "mmu", "gpu";
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| D | arm,mali-utgard.yaml | 69 - gpmmu # Geometry Processor MMU interrupt
72 - ppmmu0 # Pixel Processor X MMU interrupt (X from 0 to 7)
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| /Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 42 mmu-type:
50 Identifies the MMU address translation mode used on this
132 mmu-type = "riscv,sv39";
154 mmu-type = "riscv,sv48";
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| /Documentation/virt/kvm/arm/ |
| D | hyp-abi.txt | 32 Turn HYP/EL2 MMU off, and reset HVBAR/VBAR_EL2 to the initials
42 Mask all exceptions, disable the MMU, move the arguments into place
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| /Documentation/translations/zh_CN/arm64/ |
| D | booting.txt | 164 - 高速缓存、MMU
165 MMU 必须关闭。
207 以上对于 CPU 模式、高速缓存、MMU、架构计时器、一致性、系统寄存器的
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| /Documentation/arm/ |
| D | tcm.rst | 30 TCM location and size. Notice that this is not a MMU table: you
37 the MMU, but notice that the TCM if often used in situations where
38 the MMU is turned off. To avoid confusion the current Linux
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| D | porting.rst | 22 virtual or physical addresses here, since the MMU will be off at
31 this for you. Again, the MMU will be off.
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| /Documentation/devicetree/bindings/arm/omap/ |
| D | dmm.txt | 6 interleaving, optimizing transfer of 2D block objects, and provide MMU-like page
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| /Documentation/vm/ |
| D | z3fold.rst | 29 depend on MMU enabled and provides more predictable reclaim behavior
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| /Documentation/driver-api/ |
| D | device_link.rst | 159 * An MMU device exists alongside a busmaster device, both are in the same
160 power domain. The MMU implements DMA address translation for the busmaster
163 not bind before the MMU is bound. To achieve this, a device link with
165 to the MMU device (supplier). The effect with regards to runtime PM
166 is the same as if the MMU was the parent of the master device.
171 switch, but rather the MMU device serves the busmaster device and is
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| /Documentation/nios2/ |
| D | nios2.rst | 19 with MMU and hardware multiplier enabled.
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| /Documentation/filesystems/ |
| D | cramfs.txt | 62 segments. Both MMU and no-MMU systems are supported. This is particularly
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| /Documentation/filesystems/ext4/ |
| D | bigalloc.rst | 7 supported page size on most MMU-capable hardware. This is fortunate, as
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