| /Documentation/devicetree/bindings/spi/ |
| D | spi-img-spfi.txt | 4 - compatible: Must be "img,spfi".
5 - reg: Must contain the base address and length of the SPFI registers.
6 - interrupts: Must contain the SPFI interrupt.
7 - clocks: Must contain an entry for each entry in clock-names.
9 - clock-names: Must include the following entries:
12 - dmas: Must contain an entry for each entry in dma-names.
14 - dma-names: Must include the following entries:
17 - cs-gpios: Must specify the GPIOs used for chipselect lines.
18 - #address-cells: Must be 1.
19 - #size-cells: Must be 0.
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| D | qcom,spi-geni-qcom.txt | 11 - compatible: Must contain "qcom,geni-spi".
12 - reg: Must contain SPI register location and length.
13 - interrupts: Must contain SPI controller interrupts.
14 - clock-names: Must contain "se".
16 - #address-cells: Must be <1> to define a chip select address on
18 - #size-cells: Must be <0>.
20 SPI Controller nodes must be child of GENI based Qualcomm Universal
24 SPI slave nodes must be children of the SPI master node and conform to SPI bus
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,geni-se.txt | 11 - compatible: Must be "qcom,geni-se-qup".
12 - reg: Must contain QUP register address and length.
13 - clock-names: Must contain "m-ahb" and "s-ahb".
17 - #address-cells: Must be <1> for Serial Engine Address
18 - #size-cells: Must be <1> for Serial Engine Address Size
19 - ranges: Must be present
32 - compatible: Must be "qcom,geni-i2c".
33 - reg: Must contain QUP register address and length.
34 - interrupts: Must contain I2C interrupt.
35 - clock-names: Must contain "se".
[all …]
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| /Documentation/devicetree/bindings/usb/ |
| D | nvidia,tegra124-xusb.txt | 9 - compatible: Must be:
14 - reg: Must contain the base and length of the xHCI host registers, XUSB FPCI
16 - reg-names: Must contain the following entries:
20 - interrupts: Must contain the xHCI host interrupt and the mailbox interrupt.
21 - clocks: Must contain an entry for each entry in clock-names.
23 - clock-names: Must include the following entries:
35 - resets: Must contain an entry for each entry in reset-names.
37 - reset-names: Must include the following entries:
46 - avddio-pex-supply: PCIe/USB3 analog logic power supply. Must supply 1.05 V.
47 - dvddio-pex-supply: PCIe/USB3 digital logic power supply. Must supply 1.05 V.
[all …]
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| D | nvidia,tegra20-ehci.txt | 9 - compatible : For Tegra20, must contain "nvidia,tegra20-ehci".
10 For Tegra30, must contain "nvidia,tegra30-ehci". Otherwise, must contain
14 - clocks : Must contain one entry, for the module clock.
16 - resets : Must contain an entry for each entry in reset-names.
18 - reset-names : Must include the following entries:
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| /Documentation/arm64/ |
| D | booting.rst | 50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
52 using blocks of up to 2 megabytes in size, it must not be placed within
53 any 2M region which must be mapped with any specific attributes.
103 little-endian and must be respected. Where image_size is zero,
134 The Image must be placed text_offset bytes from a 2MB aligned base
138 At least image_size bytes from the start of the image must be free for
144 If an initrd/initramfs is passed to the kernel at boot, it must reside
153 Before jumping into the kernel, the following conditions must be met:
168 All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
170 The CPU must be in either EL2 (RECOMMENDED in order to have access to
[all …]
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| /Documentation/devicetree/bindings/display/tegra/ |
| D | nvidia,tegra20-host1x.txt | 16 - clocks: Must contain one entry, for the module clock.
18 - resets: Must contain an entry for each entry in reset-names.
20 - reset-names: Must include the following entries:
32 - clocks: Must contain one entry, for the module clock.
34 - resets: Must contain an entry for each entry in reset-names.
36 - reset-names: Must include the following entries:
45 - clocks: Must contain one entry, for the module clock.
47 - resets: Must contain an entry for each entry in reset-names.
49 - reset-names: Must include the following entries:
58 - clocks: Must contain one entry, for the module clock.
[all …]
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| /Documentation/devicetree/bindings/net/ |
| D | brcm,unimac-mdio.txt | 10 - reg-names: name(s) of the register must be "mdio" and optional "mdio_indir_rw"
11 - #size-cells: must be 1
12 - #address-cells: must be 0
15 - interrupts: must be one if the interrupt is shared with the Ethernet MAC or
16 Ethernet switch this MDIO block is integrated from, or must be two, if there
17 are two separate interrupts, first one must be "mdio done" and second must be
19 - interrupt-names: must be "mdio_done_error" when there is a share interrupt fed
20 to this hardware block, or must be "mdio_done" for the first interrupt and
23 - clock-frequency: the MDIO bus clock that must be output by the MDIO bus
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| /Documentation/virt/kvm/ |
| D | review-checklist.txt | 4 1. The patch must follow Documentation/process/coding-style.rst and
10 - the API must be documented in Documentation/virt/kvm/api.txt
11 - the API must be discoverable using KVM_CHECK_EXTENSION
13 4. New state must include support for save/restore.
15 5. New features must default to off (userspace should explicitly request them).
29 10. User/kernel interfaces and guest/host interfaces must be 64-bit clean
33 11. New guest visible features must either be documented in a hardware manual
36 12. Features must be robust against reset and kexec - for example, shared
37 host/guest memory must be unshared to prevent the host from writing to
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| /Documentation/devicetree/bindings/phy/ |
| D | phy-cadence-sierra.txt | 6 - clocks: Must contain an entry in clock-names.
8 - clock-names: Must be "phy_clk"
9 - resets: Must contain an entry for each in reset-names.
11 - reset-names: Must include "sierra_reset" and "sierra_apb".
12 "sierra_reset" must control the reset line to the PHY.
13 "sierra_apb" must control the reset line to the APB PHY
16 - #address-cells: Must be 1
17 - #size-cells: Must be 0
22 present, all sub-node optional properties must be
28 hardware strapping, and must match the configuration specified here.
[all …]
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| D | qcom-qmp-phy.txt | 31 - #address-cells: must be 1
32 - #size-cells: must be 1
33 - ranges: must be present
44 For "qcom,msm8996-qmp-pcie-phy" must contain:
46 For "qcom,msm8996-qmp-usb3-phy" must contain:
48 For "qcom,msm8998-qmp-usb3-phy" must contain:
50 For "qcom,msm8998-qmp-ufs-phy" must contain:
52 For "qcom,msm8998-qmp-pcie-phy" must contain:
54 For "qcom,sdm845-qmp-usb3-phy" must contain:
56 For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
[all …]
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| D | rockchip-pcie-phy.txt | 6 - clocks: Must contain an entry in clock-names.
8 - clock-names: Must be "refclk"
9 - resets: Must contain an entry in reset-names.
11 - reset-names: Must be "phy"
14 - #phy-cells: must be 0
17 - #phy-cells: must be 1
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| /Documentation/devicetree/bindings/clock/ |
| D | pistachio-clock.txt | 24 - compatible: Must be "img,pistachio-clk".
25 - reg: Must contain the base address and length of the core clock controller.
26 - #clock-cells: Must be 1. The single cell is the clock identifier.
28 - clocks: Must contain an entry for each clock in clock-names.
29 - clock-names: Must include "xtal" (see "External clocks") and
52 - compatible: Must be "img,pistachio-periph-clk".
53 - reg: Must contain the base address and length of the peripheral clock
55 - #clock-cells: Must be 1. The single cell is the clock identifier.
57 - clocks: Must contain an entry for each clock in clock-names.
58 - clock-names: Must include "periph_sys", the peripheral system clock generated
[all …]
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| /Documentation/devicetree/bindings/media/ |
| D | nvidia,tegra-vde.txt | 4 - compatible : Must contain one of the following values:
10 - reg : Must contain an entry for each entry in reg-names.
11 - reg-names : Must include the following entries:
21 - iram : Must contain phandle to the mmio-sram device node that represents
23 - interrupts : Must contain an entry for each entry in interrupt-names.
24 - interrupt-names : Must include the following entries:
28 - clocks : Must include the following entries:
30 - resets : Must contain an entry for each entry in reset-names.
35 - resets : Must contain an entry for each entry in reset-names.
36 - reset-names : Must include the following entries:
[all …]
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| /Documentation/devicetree/bindings/fuse/ |
| D | nvidia,tegra20-fuse.txt | 4 - compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30,
5 must contain "nvidia,tegra30-efuse". For Tegra114, must contain
6 "nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse".
7 Otherwise, must contain "nvidia,<chip>-efuse", plus one of the above, where
19 - clocks: Must contain an entry for each entry in clock-names.
21 - clock-names: Must include the following entries:
23 - resets: Must contain an entry for each entry in reset-names.
25 - reset-names: Must include the following entries:
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| /Documentation/devicetree/bindings/pci/ |
| D | ralink,rt3883-pci.txt | 7 - compatible: must be "ralink,rt3883-pci"
13 address. The value must be 1.
16 of an address. The value must be 1.
24 Value must be either "disabled" or "okay".
28 The main node must have two child nodes which describes the built-in
38 address. The value must be 0. As such, 'interrupt-map' nodes do not
42 interrupt source. The value must be 1.
53 address. The value must be 0.
56 of an address. The value must be 2.
59 interrupt source. The value must be 1.
[all …]
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| /Documentation/devicetree/bindings/dma/ |
| D | adi,axi-dmac.txt | 4 - compatible: Must be "adi,axi-dmac-1.00.a".
8 - #dma-cells: Must be 1.
11 - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
12 the channel sub-nodes the following bindings apply. They must match the
16 - #size-cells: Must be 0
17 - #address-cells: Must be 1
24 adi,destination-bus-type: Type of the source or destination bus. Must be one
32 - adi,cyclic: Must be set if the channel supports hardware cyclic DMA
34 - adi,2d: Must be set if the channel supports hardware 2D DMA transfers.
36 DMA clients connected to the AXI-DMAC DMA controller must use the format
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| D | img-mdc-dma.txt | 4 - compatible: Must be "img,pistachio-mdc-dma".
5 - reg: Must contain the base address and length of the MDC registers.
6 - interrupts: Must contain all the per-channel DMA interrupts.
7 - clocks: Must contain an entry for each entry in clock-names.
9 - clock-names: Must include the following entries:
11 - img,cr-periph: Must contain a phandle to the peripheral control syscon
13 - img,max-burst-multiplier: Must be the maximum supported burst size multiplier.
16 - #dma-cells: Must be 3:
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| /Documentation/devicetree/bindings/sound/ |
| D | qcom,lpass-cpu.txt | 8 - clocks : Must contain an entry for each entry in clock-names.
9 - clock-names : A list which must include the following entries:
22 - interrupts : Must contain an entry for each entry in
24 - interrupt-names : A list which must include the following entries:
26 - pinctrl-N : One property must exist for each entry in
29 - pinctrl-names : Must contain a "default" entry.
30 - reg : Must contain an address for each entry in reg-names.
31 - reg-names : A list which must include the following entries:
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| D | nvidia,tegra30-i2s.txt | 4 - compatible : For Tegra30, must contain "nvidia,tegra30-i2s". For Tegra124,
5 must contain "nvidia,tegra124-i2s". Otherwise, must contain
9 - clocks : Must contain one entry, for the module clock.
11 - resets : Must contain an entry for each entry in reset-names.
13 - reset-names : Must include the following entries:
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| /Documentation/devicetree/bindings/mips/img/ |
| D | pistachio.txt | 6 - compatible: Must include "img,pistachio".
11 - #address-cells: Must be 1.
12 - #size-cells: Must be 0.
16 - device_type: Must be "cpu".
17 - compatible: Must be "mti,interaptiv".
19 - clocks: Must include the CPU clock. See ../../clock/clock-bindings.txt for
37 In accordance with the MIPS UHI specification[1], the bootloader must pass the
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| /Documentation/devicetree/bindings/bus/ |
| D | renesas,bsc.txt | 12 containing the BSC must be powered on, and the functional clock
13 driving the BSC must be enabled.
19 - compatible: Must contain an SoC-specific value, and "renesas,bsc" and
24 - #address-cells, #size-cells, ranges: Must describe the mapping between
26 - reg: Must contain the base address and length to access the bus controller.
29 - interrupts: Must contain a reference to the BSC interrupt, if available.
30 - clocks: Must contain a reference to the functional clock, if available.
31 - power-domains: Must contain a reference to the PM domain, if available.
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | qcom,q6v5.txt | 9 Definition: must be one of:
20 Definition: must specify the base address and size of the qdsp6 and
26 Definition: must be "q6dsp" and "rmb"
42 must be "wdog", "fatal", "ready", "handover", "stop-ack"
45 must be "wdog", "fatal", "ready", "handover", "stop-ack",
51 Definition: must list the relative firmware image paths for mba and
69 must be "iface", "bus", "mem", "xo"
71 must be "iface", "bus", "mem", "xo", "gpll0_mss",
74 must be "iface", "bus", "mem", "xo", "gpll0_mss",
89 Definition: must be "mss_restart" for the modem sub-system
[all …]
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | samsung,exynos-adc.txt | 13 - compatible: Must be "samsung,exynos-adc-v1"
15 Must be "samsung,exynos-adc-v2" for
17 Must be "samsung,exynos3250-adc" for
19 Must be "samsung,exynos4212-adc" for
21 Must be "samsung,exynos7-adc" for
23 Must be "samsung,s3c2410-adc" for
25 Must be "samsung,s3c2416-adc" for
27 Must be "samsung,s3c2440-adc" for
29 Must be "samsung,s3c2443-adc" for
31 Must be "samsung,s3c6410-adc" for
[all …]
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| /Documentation/devicetree/bindings/ata/ |
| D | nvidia,tegra124-ahci.txt | 4 - compatible : Must be one of:
12 - clocks : Must contain an entry for each entry in clock-names.
14 - clock-names : Must include the following entries:
17 - resets : Must contain an entry for each entry in reset-names.
19 - reset-names : Must include the following entries:
23 - phys : Must contain an entry for each entry in phy-names.
25 - phy-names : Must include the following entries:
|