1NVIDIA Tegra host1x 2 3Required properties: 4- compatible: "nvidia,tegra<chip>-host1x" 5- reg: Physical base address and length of the controller's registers. 6 For pre-Tegra186, one entry describing the whole register area. 7 For Tegra186, one entry for each entry in reg-names: 8 "vm" - VM region assigned to Linux 9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor) 10- interrupts: The interrupt outputs from the controller. 11- #address-cells: The number of cells used to represent physical base addresses 12 in the host1x address space. Should be 1. 13- #size-cells: The number of cells used to represent the size of an address 14 range in the host1x address space. Should be 1. 15- ranges: The mapping of the host1x address space to the CPU address space. 16- clocks: Must contain one entry, for the module clock. 17 See ../clocks/clock-bindings.txt for details. 18- resets: Must contain an entry for each entry in reset-names. 19 See ../reset/reset.txt for details. 20- reset-names: Must include the following entries: 21 - host1x 22 23The host1x top-level node defines a number of children, each representing one 24of the following host1x client modules: 25 26- mpe: video encoder 27 28 Required properties: 29 - compatible: "nvidia,tegra<chip>-mpe" 30 - reg: Physical base address and length of the controller's registers. 31 - interrupts: The interrupt outputs from the controller. 32 - clocks: Must contain one entry, for the module clock. 33 See ../clocks/clock-bindings.txt for details. 34 - resets: Must contain an entry for each entry in reset-names. 35 See ../reset/reset.txt for details. 36 - reset-names: Must include the following entries: 37 - mpe 38 39- vi: video input 40 41 Required properties: 42 - compatible: "nvidia,tegra<chip>-vi" 43 - reg: Physical base address and length of the controller's registers. 44 - interrupts: The interrupt outputs from the controller. 45 - clocks: Must contain one entry, for the module clock. 46 See ../clocks/clock-bindings.txt for details. 47 - resets: Must contain an entry for each entry in reset-names. 48 See ../reset/reset.txt for details. 49 - reset-names: Must include the following entries: 50 - vi 51 52- epp: encoder pre-processor 53 54 Required properties: 55 - compatible: "nvidia,tegra<chip>-epp" 56 - reg: Physical base address and length of the controller's registers. 57 - interrupts: The interrupt outputs from the controller. 58 - clocks: Must contain one entry, for the module clock. 59 See ../clocks/clock-bindings.txt for details. 60 - resets: Must contain an entry for each entry in reset-names. 61 See ../reset/reset.txt for details. 62 - reset-names: Must include the following entries: 63 - epp 64 65- isp: image signal processor 66 67 Required properties: 68 - compatible: "nvidia,tegra<chip>-isp" 69 - reg: Physical base address and length of the controller's registers. 70 - interrupts: The interrupt outputs from the controller. 71 - clocks: Must contain one entry, for the module clock. 72 See ../clocks/clock-bindings.txt for details. 73 - resets: Must contain an entry for each entry in reset-names. 74 See ../reset/reset.txt for details. 75 - reset-names: Must include the following entries: 76 - isp 77 78- gr2d: 2D graphics engine 79 80 Required properties: 81 - compatible: "nvidia,tegra<chip>-gr2d" 82 - reg: Physical base address and length of the controller's registers. 83 - interrupts: The interrupt outputs from the controller. 84 - clocks: Must contain one entry, for the module clock. 85 See ../clocks/clock-bindings.txt for details. 86 - resets: Must contain an entry for each entry in reset-names. 87 See ../reset/reset.txt for details. 88 - reset-names: Must include the following entries: 89 - 2d 90 91- gr3d: 3D graphics engine 92 93 Required properties: 94 - compatible: "nvidia,tegra<chip>-gr3d" 95 - reg: Physical base address and length of the controller's registers. 96 - clocks: Must contain an entry for each entry in clock-names. 97 See ../clocks/clock-bindings.txt for details. 98 - clock-names: Must include the following entries: 99 (This property may be omitted if the only clock in the list is "3d") 100 - 3d 101 This MUST be the first entry. 102 - 3d2 (Only required on SoCs with two 3D clocks) 103 - resets: Must contain an entry for each entry in reset-names. 104 See ../reset/reset.txt for details. 105 - reset-names: Must include the following entries: 106 - 3d 107 - 3d2 (Only required on SoCs with two 3D clocks) 108 109- dc: display controller 110 111 Required properties: 112 - compatible: "nvidia,tegra<chip>-dc" 113 - reg: Physical base address and length of the controller's registers. 114 - interrupts: The interrupt outputs from the controller. 115 - clocks: Must contain an entry for each entry in clock-names. 116 See ../clocks/clock-bindings.txt for details. 117 - clock-names: Must include the following entries: 118 - dc 119 This MUST be the first entry. 120 - parent 121 - resets: Must contain an entry for each entry in reset-names. 122 See ../reset/reset.txt for details. 123 - reset-names: Must include the following entries: 124 - dc 125 - nvidia,head: The number of the display controller head. This is used to 126 setup the various types of output to receive video data from the given 127 head. 128 129 Each display controller node has a child node, named "rgb", that represents 130 the RGB output associated with the controller. It can take the following 131 optional properties: 132 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 133 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 134 - nvidia,edid: supplies a binary EDID blob 135 - nvidia,panel: phandle of a display panel 136 137- hdmi: High Definition Multimedia Interface 138 139 Required properties: 140 - compatible: "nvidia,tegra<chip>-hdmi" 141 - reg: Physical base address and length of the controller's registers. 142 - interrupts: The interrupt outputs from the controller. 143 - hdmi-supply: supply for the +5V HDMI connector pin 144 - vdd-supply: regulator for supply voltage 145 - pll-supply: regulator for PLL 146 - clocks: Must contain an entry for each entry in clock-names. 147 See ../clocks/clock-bindings.txt for details. 148 - clock-names: Must include the following entries: 149 - hdmi 150 This MUST be the first entry. 151 - parent 152 - resets: Must contain an entry for each entry in reset-names. 153 See ../reset/reset.txt for details. 154 - reset-names: Must include the following entries: 155 - hdmi 156 157 Optional properties: 158 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 159 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 160 - nvidia,edid: supplies a binary EDID blob 161 - nvidia,panel: phandle of a display panel 162 163- tvo: TV encoder output 164 165 Required properties: 166 - compatible: "nvidia,tegra<chip>-tvo" 167 - reg: Physical base address and length of the controller's registers. 168 - interrupts: The interrupt outputs from the controller. 169 - clocks: Must contain one entry, for the module clock. 170 See ../clocks/clock-bindings.txt for details. 171 172- dsi: display serial interface 173 174 Required properties: 175 - compatible: "nvidia,tegra<chip>-dsi" 176 - reg: Physical base address and length of the controller's registers. 177 - clocks: Must contain an entry for each entry in clock-names. 178 See ../clocks/clock-bindings.txt for details. 179 - clock-names: Must include the following entries: 180 - dsi 181 This MUST be the first entry. 182 - lp 183 - parent 184 - resets: Must contain an entry for each entry in reset-names. 185 See ../reset/reset.txt for details. 186 - reset-names: Must include the following entries: 187 - dsi 188 - avdd-dsi-supply: phandle of a supply that powers the DSI controller 189 - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying 190 which pads are used by this DSI output and need to be calibrated. See also 191 ../display/tegra/nvidia,tegra114-mipi.txt. 192 193 Optional properties: 194 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 195 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 196 - nvidia,edid: supplies a binary EDID blob 197 - nvidia,panel: phandle of a display panel 198 - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang 199 up with in order to support up to 8 data lanes 200 201- sor: serial output resource 202 203 Required properties: 204 - compatible: Should be: 205 - "nvidia,tegra124-sor": for Tegra124 and Tegra132 206 - "nvidia,tegra132-sor": for Tegra132 207 - "nvidia,tegra210-sor": for Tegra210 208 - "nvidia,tegra210-sor1": for Tegra210 209 - "nvidia,tegra186-sor": for Tegra186 210 - "nvidia,tegra186-sor1": for Tegra186 211 - reg: Physical base address and length of the controller's registers. 212 - interrupts: The interrupt outputs from the controller. 213 - clocks: Must contain an entry for each entry in clock-names. 214 See ../clocks/clock-bindings.txt for details. 215 - clock-names: Must include the following entries: 216 - sor: clock input for the SOR hardware 217 - out: SOR output clock 218 - parent: input for the pixel clock 219 - dp: reference clock for the SOR clock 220 - safe: safe reference for the SOR clock during power up 221 222 For Tegra186 and later: 223 - pad: SOR pad output clock (on Tegra186 and later) 224 225 Obsolete: 226 - source: source clock for the SOR clock (obsolete, use "out" instead) 227 228 - resets: Must contain an entry for each entry in reset-names. 229 See ../reset/reset.txt for details. 230 - reset-names: Must include the following entries: 231 - sor 232 233 Required properties on Tegra186 and later: 234 - nvidia,interface: index of the SOR interface 235 236 Optional properties: 237 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 238 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 239 - nvidia,edid: supplies a binary EDID blob 240 - nvidia,panel: phandle of a display panel 241 - nvidia,xbar-cfg: 5 cells containing the crossbar configuration. Each lane 242 of the SOR, identified by the cell's index, is mapped via the crossbar to 243 the pad specified by the cell's value. 244 245 Optional properties when driving an eDP output: 246 - nvidia,dpaux: phandle to a DispayPort AUX interface 247 248- dpaux: DisplayPort AUX interface 249 - compatible : Should contain one of the following: 250 - "nvidia,tegra124-dpaux": for Tegra124 and Tegra132 251 - "nvidia,tegra210-dpaux": for Tegra210 252 - reg: Physical base address and length of the controller's registers. 253 - interrupts: The interrupt outputs from the controller. 254 - clocks: Must contain an entry for each entry in clock-names. 255 See ../clocks/clock-bindings.txt for details. 256 - clock-names: Must include the following entries: 257 - dpaux: clock input for the DPAUX hardware 258 - parent: reference clock 259 - resets: Must contain an entry for each entry in reset-names. 260 See ../reset/reset.txt for details. 261 - reset-names: Must include the following entries: 262 - dpaux 263 - vdd-supply: phandle of a supply that powers the DisplayPort link 264 - i2c-bus: Subnode where I2C slave devices are listed. This subnode 265 must be always present. If there are no I2C slave devices, an empty 266 node should be added. See ../../i2c/i2c.txt for more information. 267 268 See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information 269 regarding the DPAUX pad controller bindings. 270 271- vic: Video Image Compositor 272 - compatible : "nvidia,tegra<chip>-vic" 273 - reg: Physical base address and length of the controller's registers. 274 - interrupts: The interrupt outputs from the controller. 275 - clocks: Must contain an entry for each entry in clock-names. 276 See ../clocks/clock-bindings.txt for details. 277 - clock-names: Must include the following entries: 278 - vic: clock input for the VIC hardware 279 - resets: Must contain an entry for each entry in reset-names. 280 See ../reset/reset.txt for details. 281 - reset-names: Must include the following entries: 282 - vic 283 284Example: 285 286/ { 287 ... 288 289 host1x { 290 compatible = "nvidia,tegra20-host1x", "simple-bus"; 291 reg = <0x50000000 0x00024000>; 292 interrupts = <0 65 0x04 /* mpcore syncpt */ 293 0 67 0x04>; /* mpcore general */ 294 clocks = <&tegra_car TEGRA20_CLK_HOST1X>; 295 resets = <&tegra_car 28>; 296 reset-names = "host1x"; 297 298 #address-cells = <1>; 299 #size-cells = <1>; 300 301 ranges = <0x54000000 0x54000000 0x04000000>; 302 303 mpe { 304 compatible = "nvidia,tegra20-mpe"; 305 reg = <0x54040000 0x00040000>; 306 interrupts = <0 68 0x04>; 307 clocks = <&tegra_car TEGRA20_CLK_MPE>; 308 resets = <&tegra_car 60>; 309 reset-names = "mpe"; 310 }; 311 312 vi { 313 compatible = "nvidia,tegra20-vi"; 314 reg = <0x54080000 0x00040000>; 315 interrupts = <0 69 0x04>; 316 clocks = <&tegra_car TEGRA20_CLK_VI>; 317 resets = <&tegra_car 100>; 318 reset-names = "vi"; 319 }; 320 321 epp { 322 compatible = "nvidia,tegra20-epp"; 323 reg = <0x540c0000 0x00040000>; 324 interrupts = <0 70 0x04>; 325 clocks = <&tegra_car TEGRA20_CLK_EPP>; 326 resets = <&tegra_car 19>; 327 reset-names = "epp"; 328 }; 329 330 isp { 331 compatible = "nvidia,tegra20-isp"; 332 reg = <0x54100000 0x00040000>; 333 interrupts = <0 71 0x04>; 334 clocks = <&tegra_car TEGRA20_CLK_ISP>; 335 resets = <&tegra_car 23>; 336 reset-names = "isp"; 337 }; 338 339 gr2d { 340 compatible = "nvidia,tegra20-gr2d"; 341 reg = <0x54140000 0x00040000>; 342 interrupts = <0 72 0x04>; 343 clocks = <&tegra_car TEGRA20_CLK_GR2D>; 344 resets = <&tegra_car 21>; 345 reset-names = "2d"; 346 }; 347 348 gr3d { 349 compatible = "nvidia,tegra20-gr3d"; 350 reg = <0x54180000 0x00040000>; 351 clocks = <&tegra_car TEGRA20_CLK_GR3D>; 352 resets = <&tegra_car 24>; 353 reset-names = "3d"; 354 }; 355 356 dc@54200000 { 357 compatible = "nvidia,tegra20-dc"; 358 reg = <0x54200000 0x00040000>; 359 interrupts = <0 73 0x04>; 360 clocks = <&tegra_car TEGRA20_CLK_DISP1>, 361 <&tegra_car TEGRA20_CLK_PLL_P>; 362 clock-names = "dc", "parent"; 363 resets = <&tegra_car 27>; 364 reset-names = "dc"; 365 366 rgb { 367 status = "disabled"; 368 }; 369 }; 370 371 dc@54240000 { 372 compatible = "nvidia,tegra20-dc"; 373 reg = <0x54240000 0x00040000>; 374 interrupts = <0 74 0x04>; 375 clocks = <&tegra_car TEGRA20_CLK_DISP2>, 376 <&tegra_car TEGRA20_CLK_PLL_P>; 377 clock-names = "dc", "parent"; 378 resets = <&tegra_car 26>; 379 reset-names = "dc"; 380 381 rgb { 382 status = "disabled"; 383 }; 384 }; 385 386 hdmi { 387 compatible = "nvidia,tegra20-hdmi"; 388 reg = <0x54280000 0x00040000>; 389 interrupts = <0 75 0x04>; 390 clocks = <&tegra_car TEGRA20_CLK_HDMI>, 391 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 392 clock-names = "hdmi", "parent"; 393 resets = <&tegra_car 51>; 394 reset-names = "hdmi"; 395 status = "disabled"; 396 }; 397 398 tvo { 399 compatible = "nvidia,tegra20-tvo"; 400 reg = <0x542c0000 0x00040000>; 401 interrupts = <0 76 0x04>; 402 clocks = <&tegra_car TEGRA20_CLK_TVO>; 403 status = "disabled"; 404 }; 405 406 dsi { 407 compatible = "nvidia,tegra20-dsi"; 408 reg = <0x54300000 0x00040000>; 409 clocks = <&tegra_car TEGRA20_CLK_DSI>, 410 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 411 clock-names = "dsi", "parent"; 412 resets = <&tegra_car 48>; 413 reset-names = "dsi"; 414 status = "disabled"; 415 }; 416 }; 417 418 ... 419}; 420