Home
last modified time | relevance | path

Searched +full:non +full:- +full:secure (Results 1 – 25 of 59) sorted by relevance

123

/Documentation/devicetree/bindings/arm/
Dsecure.txt1 * ARM Secure world bindings
4 "Normal" and "Secure". Most devicetree consumers (including the Linux
6 world or the Secure world. However some devicetree consumers are
8 visible only in the Secure address space, only in the Normal address
10 virtual machine which boots Secure firmware and wants to tell the
13 The general principle of the naming scheme for Secure world bindings
14 is that any property that needs a different value in the Secure world
15 can be supported by prefixing the property name with "secure-". So for
16 instance "secure-foo" would override "foo". For property names with
17 a vendor prefix, the Secure variant of "vendor,foo" would be
[all …]
Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - arm,armv8-pmuv3
24 - arm,cortex-a73-pmu
[all …]
Djuno,scpi.txt5 ------------------------------------
8 - compatible : should be "arm,juno-sram-ns" for Non-secure SRAM
10 Each sub-node represents the reserved area for SCPI.
12 Required sub-node properties:
13 - reg : The base offset and size of the reserved area with the SRAM
14 - compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based
18 --------------------------------------------------------------
20 - compatible : should be "arm,scpi-sensors".
21 - #thermal-sensor-cells: should be set to 1.
/Documentation/devicetree/bindings/iommu/
Dqcom,iommu.txt3 Qualcomm "B" family devices which are not compatible with arm-smmu have
6 to non-secure vs secure interrupt line.
10 - compatible : Should be one of:
12 "qcom,msm8916-iommu"
14 Followed by "qcom,msm-iommu-v1".
16 - clock-names : Should be a pair of "iface" (required for IOMMUs
20 - clocks : Phandles for respective clocks described by
21 clock-names.
23 - #address-cells : must be 1.
25 - #size-cells : must be 1.
[all …]
Dmsm,iommu-v0.txt5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9 - compatible: Must contain "qcom,apq8064-iommu".
10 - reg: Base address and size of the IOMMU registers.
11 - interrupts: Specifiers for the MMU fault interrupts. For instances that
12 support secure mode two interrupts must be specified, for non-secure and
13 secure mode, in that order. For instances that don't support secure mode a
15 - #iommu-cells: The number of cells needed to specify the stream id. This
17 - qcom,ncb: The total number of context banks in the IOMMU.
18 - clocks : List of clocks to be used during SMMU register access. See
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
[all …]
Drenesas,ipmmu-vmsa.txt1 * Renesas VMSA-Compatible IOMMU
5 connected to the IPMMU through a port called micro-TLB.
10 - compatible: Must contain SoC-specific and generic entry below in case
11 the device is compatible with the R-Car Gen2 VMSA-compatible IPMMU.
13 - "renesas,ipmmu-r8a73a4" for the R8A73A4 (R-Mobile APE6) IPMMU.
14 - "renesas,ipmmu-r8a7743" for the R8A7743 (RZ/G1M) IPMMU.
15 - "renesas,ipmmu-r8a7744" for the R8A7744 (RZ/G1N) IPMMU.
16 - "renesas,ipmmu-r8a7745" for the R8A7745 (RZ/G1E) IPMMU.
17 - "renesas,ipmmu-r8a774a1" for the R8A774A1 (RZ/G2M) IPMMU.
18 - "renesas,ipmmu-r8a774c0" for the R8A774C0 (RZ/G2E) IPMMU.
[all …]
Darm,smmu.txt12 - compatible : Should be one of:
14 "arm,smmu-v1"
15 "arm,smmu-v2"
16 "arm,mmu-400"
17 "arm,mmu-401"
18 "arm,mmu-500"
19 "cavium,smmu-v2"
20 "qcom,smmu-v2"
25 Qcom SoCs must contain, as below, SoC-specific compatibles
26 along with "qcom,smmu-v2":
[all …]
Darm,smmu-v3.txt4 revisions, replacing the MMIO register interface with in-memory command
10 - compatible : Should include:
12 * "arm,smmu-v3" for any SMMUv3 compliant
16 - reg : Base address and size of the SMMU.
18 - interrupts : Non-secure interrupt list describing the wired
20 interrupt-names. If no wired interrupts are
23 - interrupt-names : When the interrupts property is present, should
25 * "eventq" - Event Queue not empty
26 * "priq" - PRI Queue not empty
27 * "cmdq-sync" - CMD_SYNC complete
[all …]
/Documentation/devicetree/bindings/sram/
Dsamsung-sram.txt2 ------------------------------------
4 Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
8 Therefore reserved section sub-nodes have to be added to the mmio-sram
9 declaration. These nodes are of two types depending upon secure or
10 non-secure execution environment.
12 Required sub-node properties:
13 - compatible : depending upon boot mode, should be
14 "samsung,exynos4210-sysram" : for Secure SYSRAM
15 "samsung,exynos4210-sysram-ns" : for Non-secure SYSRAM
17 The rest of the properties should follow the generic mmio-sram discription
[all …]
/Documentation/devicetree/bindings/misc/
Dbrcm,kona-smc.txt1 Broadcom Secure Monitor Bounce buffer
2 -----------------------------------------------------
4 used for non-secure to secure communications.
7 - compatible : "brcm,kona-smc"
8 - DEPRECATED: compatible : "bcm,kona-smc"
9 - reg : Location and size of bounce buffer
13 compatible = "brcm,bcm11351-smc", "brcm,kona-smc";
/Documentation/devicetree/bindings/clock/
Dfujitsu,mb86s70-crg11.txt2 -----------------------------------
5 - compatible : Shall contain "fujitsu,mb86s70-crg11"
6 - #clock-cells : Shall be 3 {cntrlr domain port}
13 compatible = "fujitsu,mb86s70-crg11";
14 #clock-cells = <3>;
18 #mbox-cells = <1>;
21 interrupts = <0 36 4>, /* LP Non-Sec */
22 <0 35 4>, /* HP Non-Sec */
23 <0 37 4>; /* Secure */
25 clock-names = "clk";
/Documentation/arm/samsung/
Dbootloader-interface.rst14 In the document "boot loader" means any of following: U-boot, proprietary
19 1. Non-Secure mode
37 2. Secure mode
65 3. Other (regardless of secure/non-secure mode)
72 0x0908 Non-zero Secondary CPU boot up indicator
79 AFTR - ARM Off Top Running, a low power mode, Cortex cores and many other
81 MCPM - Multi-Cluster Power Management
/Documentation/devicetree/bindings/soc/rockchip/
Dgrf.txt7 - GRF, used for general non-secure system,
8 - SGRF, used for general secure system,
9 - PMUGRF, used for always on system
15 - compatible: GRF should be one of the following:
16 - "rockchip,px30-grf", "syscon": for px30
17 - "rockchip,rk3036-grf", "syscon": for rk3036
18 - "rockchip,rk3066-grf", "syscon": for rk3066
19 - "rockchip,rk3188-grf", "syscon": for rk3188
20 - "rockchip,rk3228-grf", "syscon": for rk3228
21 - "rockchip,rk3288-grf", "syscon": for rk3288
[all …]
/Documentation/arm64/
Dbooting.rst13 (EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
14 counterpart. EL2 is the hypervisor level and exists only in non-secure
15 mode. EL3 is the highest priority level and exists only in secure mode.
19 is passed to the Linux kernel. This may include secure monitor and
33 ---------------------------
46 -------------------------
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
59 ------------------------------
71 ------------------------
75 The decompressed kernel image contains a 64-byte header as follows::
[all …]
/Documentation/devicetree/bindings/arm/samsung/
Dsamsung-boards.txt4 - compatible = should be one or more of the following.
5 - "samsung,aries" - for S5PV210-based Samsung Aries board.
6 - "samsung,fascinate4g" - for S5PV210-based Samsung Galaxy S Fascinate 4G (SGH-T959P) board.
7 - "samsung,galaxys" - for S5PV210-based Samsung Galaxy S (i9000) board.
8 - "samsung,artik5" - for Exynos3250-based Samsung ARTIK5 module.
9 - "samsung,artik5-eval" - for Exynos3250-based Samsung ARTIK5 eval board.
10 - "samsung,monk" - for Exynos3250-based Samsung Simband board.
11 - "samsung,rinato" - for Exynos3250-based Samsung Gear2 board.
12 - "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board.
13 - "samsung,trats" - for Exynos4210-based Tizen Reference board.
[all …]
/Documentation/devicetree/bindings/nvmem/
Dsnvs-lpgpr.txt2 and i.MX7 Secure Non-Volatile Storage.
4 This DT node should be represented as a sub-node of a "syscon",
5 "simple-mfd" node.
8 - compatible: should be one of the fallowing variants:
9 "fsl,imx6q-snvs-lpgpr" for Freescale i.MX6Q/D/DL/S
10 "fsl,imx6ul-snvs-lpgpr" for Freescale i.MX6UL
11 "fsl,imx7d-snvs-lpgpr" for Freescale i.MX7D/S
15 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
18 snvs_lpgpr: snvs-lpgpr {
19 compatible = "fsl,imx6q-snvs-lpgpr";
/Documentation/powerpc/
Dultravisor.rst1 .. SPDX-License-Identifier: GPL-2.0
15 POWER 9 that enables Secure Virtual Machines (SVMs). DD2.3 chips
16 (PVR=0x004e1203) or greater will be PEF-capable. A new ISA release
25 +------------------+
29 +------------------+
31 +------------------+
33 +------------------+
35 +------------------+
56 process is running in secure mode, MSR(S) bit 41. MSR(S)=1, process
57 is in secure mode, MSR(s)=0 process is in normal mode.
[all …]
/Documentation/arm/
Dfirmware.rst2 Interface for registering and calling firmware-specific operations for ARM
7 Some boards are running with secure firmware running in TrustZone secure
18 The ops pointer must be non-NULL. More information about struct firmware_ops
27 ((firmware_ops->op) ? firmware_ops->op(__VA_ARGS__) : (-ENOSYS))
30 -ENOSYS to signal that given operation is not available (for example, to allow
69 if (call_firmware_op(cpu_boot, cpu) == -ENOSYS)
/Documentation/devicetree/bindings/timer/
Darm,arch_timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
24 - items:
25 - enum:
[all …]
/Documentation/devicetree/bindings/interrupt-controller/
Dmarvell,icu.txt2 --------------------------------
5 responsible for collecting all wired-interrupt sources in the CP and
13 - compatible: Should be "marvell,cp110-icu"
15 - reg: Should contain ICU registers location and length.
22 - compatible: Should be one of:
23 * "marvell,cp110-icu-nsr"
24 * "marvell,cp110-icu-sr"
25 * "marvell,cp110-icu-sei"
26 * "marvell,cp110-icu-rei"
28 - #interrupt-cells: Specifies the number of cells needed to encode an
[all …]
/Documentation/trace/
Dcoresight-cpu-debug.rst9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
20 to sample CPU program counter, secure state and exception level, etc; usually
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
29 --------------
31 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
32 registers to decide if sample-based profiling is implemented or not. On some
[all …]
/Documentation/ABI/testing/
Dsysfs-bus-thunderbolt4 Contact: thunderbolt-software@lists.01.org
27 Contact: thunderbolt-software@lists.01.org
36 Contact: thunderbolt-software@lists.01.org
43 secure: Require devices that support secure connect at
54 Contact: thunderbolt-software@lists.01.org
79 Contact: thunderbolt-software@lists.01.org
86 Contact: thunderbolt-software@lists.01.org
87 Description: When a devices supports Thunderbolt secure connect it will
89 authorization to use the secure connection method instead.
96 Contact: thunderbolt-software@lists.01.org
[all …]
/Documentation/admin-guide/
Dthunderbolt.rst5 should be a userspace tool that handles all the low-level details, keeps
9 found in ``Documentation/ABI/testing/sysfs-bus-thunderbolt``.
13 ``/etc/udev/rules.d/99-local.rules``::
22 -----------------------------------
43 secure
45 addition to UUID the device (if it supports secure connect) is sent
65 If the security level reads as ``user`` or ``secure`` the connected
74 Authorizing devices when security level is ``user`` or ``secure``
75 -----------------------------------------------------------------
78 /sys/bus/thunderbolt/devices/0-1/authorized - 0
[all …]
/Documentation/x86/
Damd-memory-encryption.rst1 .. SPDX-License-Identifier: GPL-2.0
7 Secure Memory Encryption (SME) and Secure Encrypted Virtualization (SEV) are
19 memory. Private memory is encrypted with the guest-specific key, while shared
39 is operating in 64-bit or 32-bit PAE mode, in all other modes the SEV hardware
78 - Supported:
81 - Enabled:
84 - Active:
87 kernel is non-zero).
/Documentation/devicetree/bindings/mmc/
Dsdhci-sprd.txt1 * Spreadtrum SDHCI controller (sdhci-sprd)
3 The Secure Digital (SD) Host controller on Spreadtrum SoCs provides an interface
7 and the properties used by the sdhci-sprd driver.
10 - compatible: Should contain "sprd,sdhci-r11".
11 - reg: physical base address of the controller and length.
12 - interrupts: Interrupts used by the SDHCI controller.
13 - clocks: Should contain phandle for the clock feeding the SDHCI controller
14 - clock-names: Should contain the following:
15 "sdio" - SDIO source clock (required)
16 "enable" - gate clock which used for enabling/disabling the device (required)
[all …]

123