Searched full:addr (Results 1 – 25 of 153) sorted by relevance
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| /Documentation/devicetree/bindings/leds/ |
| D | leds-netxbig.txt | 15 - mode-addr: Mode register address on gpio-ext bus.
18 - bright-addr: Brightness register address on gpio-ext bus.
37 mode-addr = <0>;
42 bright-addr = <1>;
47 mode-addr = <0>;
51 bright-addr = <1>;
56 mode-addr = <3>;
61 bright-addr = <2>;
66 mode-addr = <3>;
70 bright-addr = <2>;
[all …]
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| /Documentation/networking/ |
| D | cops.txt | 42 inet addr:192.168.1.2 Bcast:192.168.1.255 Mask:255.255.255.0
52 dummy -seed -phase 2 -net 2000 -addr 2000.10 -zone "1033"
53 lt0 -seed -phase 1 -net 1000 -addr 1000.50 -zone "1033"
56 eth0 -seed -phase 2 -net 3000 -addr 3000.20 -zone "1033"
57 lt0 -seed -phase 1 -net 1000 -addr 1000.50 -zone "1033"
61 lt0 -seed -phase 1 -net 1000 -addr 1000.10 -zone "LocalTalk1"
62 lt1 -seed -phase 1 -net 2000 -addr 2000.20 -zone "LocalTalk2"
63 eth0 -seed -phase 2 -net 3000 -addr 3000.30 -zone "EtherTalk"
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| D | j1939.rst | 178 __u8 addr;
190 can_addr.j1939.addr contains the address.
194 I.e. only packets with a matching PGN are received. If an ADDR or NAME is set
195 it is used as a receive filter, too. It will match the destination NAME or ADDR
202 packets. If ADDR or NAME is set it will be used as the default destination ADDR
203 or NAME. Further a set ADDR or NAME during connect(2) is used as a receive
204 filter. It will match the source NAME or ADDR of the incoming packet.
211 the corresponding ADDR is used. If can_addr.j1939.name is not set (== 0),
212 can_addr.j1939.addr is used.
310 j1939.addr member will be ignored.
[all …]
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| D | phonet.txt | 97 struct sockaddr_pn addr = { .spn_family = AF_PHONET, };
99 socklen_t addrlen = sizeof(addr);
103 bind(fd, (struct sockaddr *)&addr, sizeof(addr));
106 sendto(fd, msg, msglen, 0, (struct sockaddr *)&addr, sizeof(addr));
108 (struct sockaddr *)&addr, &addrlen);
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpc5200.txt | 76 cdm@<addr> fsl,mpc5200-cdm Clock Distribution
77 interrupt-controller@<addr> fsl,mpc5200-pic need an interrupt
79 bestcomm@<addr> fsl,mpc5200-bestcomm Bestcomm DMA controller
84 timer@<addr> fsl,mpc5200-gpt General purpose timers
85 gpio@<addr> fsl,mpc5200-gpio MPC5200 simple gpio controller
86 gpio@<addr> fsl,mpc5200-gpio-wkup MPC5200 wakeup gpio controller
87 rtc@<addr> fsl,mpc5200-rtc Real time clock
88 mscan@<addr> fsl,mpc5200-mscan CAN bus controller
89 pci@<addr> fsl,mpc5200-pci PCI bridge
90 serial@<addr> fsl,mpc5200-psc-uart PSC in serial mode
[all …]
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| /Documentation/i2c/ |
| D | i2c-protocol.rst | 15 Addr (7 bits): I2C 7 bit address. Note that this can be expanded as usual to
33 S Addr Wr [A] Data [A] Data [A] ... [A] Data [A] P
41 S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P
53 S Addr Rd [A] [Data] NA S Addr Wr [A] Data [A] P
73 In a combined transaction, no 'S Addr Wr/Rd [A]' is generated at some
77 S Addr Rd [A] [Data] NA Data [A] P
80 we do not generate Addr, but we do generate the startbit S. This will
93 S Addr Rd [A] Data [A] Data [A] ... [A] Data [A] P
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| D | smbus-protocol.rst | 42 Addr (7 bits): I2C 7 bit address. Note that this can be expanded as usual to
60 A Addr Rd/Wr [A] P
73 S Addr Rd [A] [Data] NA P
86 S Addr Wr [A] Data [A] P
97 S Addr Wr [A] Comm [A] S Addr Rd [A] [Data] NA P
109 S Addr Wr [A] Comm [A] S Addr Rd [A] [DataLow] A [DataHigh] NA P
127 S Addr Wr [A] Comm [A] Data [A] P
139 S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A] P
154 S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A]
155 S Addr Rd [A] [DataLow] A [DataHigh] NA P
[all …]
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| /Documentation/devicetree/bindings/sound/ |
| D | ssm4567.txt | 7 - reg : the I2C address of the device. This will either be 0x34 (LR_SEL/ADDR connected to AGND),
8 0x35 (LR_SEL/ADDR connected to IOVDD) or 0x36 (LR_SEL/ADDR open).
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| D | ssm2518.txt | 7 - reg : the I2C address of the device. This will either be 0x34 (ADDR pin low)
8 or 0x35 (ADDR pin high)
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| /Documentation/devicetree/bindings/nios2/ |
| D | nios2.txt | 29 - altr,reset-addr: Specifies CPU reset address
30 - altr,fast-tlb-miss-addr: Specifies CPU fast TLB miss exception address
31 - altr,exception-addr: Specifies CPU exception address
57 altr,reset-addr = <0xc2800000>;
58 altr,fast-tlb-miss-addr = <0xc7fff400>;
59 altr,exception-addr = <0xd0000020>;
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-moxtet-devices | 1 What: /sys/bus/moxtet/devices/moxtet-<name>.<addr>/module_description
7 What: /sys/bus/moxtet/devices/moxtet-<name>.<addr>/module_id
13 What: /sys/bus/moxtet/devices/moxtet-<name>.<addr>/module_name
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| /Documentation/devicetree/bindings/leds/backlight/ |
| D | lp855x.txt | 13 - rom-addr: Register address of ROM area to be updated (u8)
30 rom-addr = /bits/ 8 <0x14>;
36 rom-addr = /bits/ 8 <0x15>;
42 rom-addr = /bits/ 8 <0x19>;
69 rom-addr = /bits/ 8 <0x14>;
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| /Documentation/devicetree/bindings/mtd/ |
| D | fsl-upm-nand.txt | 6 - fsl,upm-addr-offset : UPM pattern offset for the address latch.
13 - fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
31 fsl,upm-addr-offset = <16>;
51 fsl,upm-addr-offset = <0x10>;
54 fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
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| /Documentation/networking/dsa/ |
| D | configuration.rst | 87 ip addr add 192.0.2.1/30 dev lan1
88 ip addr add 192.0.2.5/30 dev lan2
89 ip addr add 192.0.2.9/30 dev lan3
121 ip addr add 192.0.2.129/25 dev br0
140 ip addr add 192.0.2.1/30 dev wan
150 ip addr add 192.0.2.129/25 dev br0
203 ip addr add 192.0.2.1/30 dev eth0.1
204 ip addr add 192.0.2.5/30 dev eth0.2
205 ip addr add 192.0.2.9/30 dev eth0.3
246 ip addr add 192.0.2.129/25 dev br0
[all …]
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| D | b53.rst | 100 ip addr add 192.0.2.1/30 dev eth0.1
101 ip addr add 192.0.2.5/30 dev eth0.2
102 ip addr add 192.0.2.9/30 dev eth0.3
138 ip addr add 192.0.2.129/25 dev br0
179 ip addr add 192.0.2.1/30 dev eth0.2
180 ip addr add 192.0.2.129/25 dev br0
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| /Documentation/virt/kvm/devices/ |
| D | vfio.txt | 19 kvm_device_attr.addr points to an int32_t file descriptor
22 kvm_device_attr.addr points to an int32_t file descriptor
26 kvm_device_attr.addr points to a struct:
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| D | s390_flic.txt | 25 attr->addr contains the pointer to the buffer and attr->attr contains
39 attr->addr contains the userspace address of the buffer into which all
50 attr->addr (address) and attr->attr (length).
93 __u64 addr;
103 perform a gmap translation for the guest address provided in addr,
110 release a userspace page for the translated address specified in addr
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| D | xive.txt | 85 The kvm_device_attr.addr points to a __u64 value:
93 -EFAULT: Invalid user pointer for attr->addr.
100 The kvm_device_attr.addr points to a __u64 value:
112 -EFAULT: Invalid user pointer for attr->addr.
124 The kvm_device_attr.addr points to :
148 -EFAULT: Invalid user pointer for attr->addr.
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| /Documentation/devicetree/bindings/arm/ |
| D | cpus.yaml | 204 cpu-release-addr:
350 cpu-release-addr = <0 0x20000000>;
358 cpu-release-addr = <0 0x20000000>;
366 cpu-release-addr = <0 0x20000000>;
374 cpu-release-addr = <0 0x20000000>;
382 cpu-release-addr = <0 0x20000000>;
390 cpu-release-addr = <0 0x20000000>;
398 cpu-release-addr = <0 0x20000000>;
406 cpu-release-addr = <0 0x20000000>;
414 cpu-release-addr = <0 0x20000000>;
[all …]
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| /Documentation/powerpc/ |
| D | ptrace.rst | 76 uint64_t addr;
102 p.addr = (uint64_t) address;
112 p.addr = (uint64_t) address;
122 p.addr = (uint64_t) address;
132 p.addr = (uint64_t) begin_range;
145 p.addr = (uint64_t) begin_range;
147 * addr2 - addr <= 8 Bytes.
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| /Documentation/devicetree/bindings/cpu/ |
| D | cpu-topology.txt | 281 cpu-release-addr = <0 0x20000000>;
289 cpu-release-addr = <0 0x20000000>;
297 cpu-release-addr = <0 0x20000000>;
305 cpu-release-addr = <0 0x20000000>;
313 cpu-release-addr = <0 0x20000000>;
321 cpu-release-addr = <0 0x20000000>;
329 cpu-release-addr = <0 0x20000000>;
337 cpu-release-addr = <0 0x20000000>;
345 cpu-release-addr = <0 0x20000000>;
353 cpu-release-addr = <0 0x20000000>;
[all …]
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| /Documentation/devicetree/bindings/arm/altera/ |
| D | socfpga-system.txt | 6 - cpu1-start-addr : CPU1 start address in hex.
12 cpu1-start-addr = <0xffd080c4>;
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| /Documentation/devicetree/bindings/gpio/ |
| D | netxbig-gpio-ext.txt | 6 - addr-gpios: GPIOs representing the address register (LSB -> MSB).
15 addr-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH
|
| /Documentation/core-api/ |
| D | atomic_ops.rst | 451 void set_bit(unsigned long nr, volatile unsigned long *addr);
452 void clear_bit(unsigned long nr, volatile unsigned long *addr);
453 void change_bit(unsigned long nr, volatile unsigned long *addr);
456 indicated by "nr" on the bit mask pointed to by "ADDR".
461 int test_and_set_bit(unsigned long nr, volatile unsigned long *addr);
462 int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr);
463 int test_and_change_bit(unsigned long nr, volatile unsigned long *addr);
505 int test_bit(unsigned long nr, __const__ volatile unsigned long *addr);
508 pointed to by "addr".
537 int test_and_set_bit_lock(unsigned long nr, unsigned long *addr);
[all …]
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | mcp3911.txt | 16 - microchip,device-addr: Device address when multiple MCP3911 chips are present on the
27 microchip,device-addr = <0>;
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