Searched full:apb (Results 1 – 25 of 71) sorted by relevance
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | csky,apb-intc.txt | 2 C-SKY APB Interrupt Controller
5 C-SKY APB Interrupt Controller is a simple soc interrupt controller
6 on the apb bus and we only use it as root irq controller.
8 - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums.
9 - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported.
16 Description: Describes APB interrupt controller
23 Definition: must be "csky,apb-intc"
24 "csky,dual-apb-intc"
44 compatible = "csky,apb-intc";
51 compatible = "csky,dual-apb-intc";
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| D | snps,dw-apb-ictl.txt | 1 Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
3 Synopsys DesignWare provides interrupt controller IP for APB known as
5 APB bus, e.g. Marvell Armada 1500.
8 - compatible: shall be "snps,dw-apb-ictl"
25 compatible = "snps,dw-apb-ictl";
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| /Documentation/devicetree/bindings/rtc/ |
| D | dw-apb.txt | 1 * Designware APB timer
5 "snps,dw-apb-timer"
6 "snps,dw-apb-timer-sp" <DEPRECATED>
7 "snps,dw-apb-timer-osc" <DEPRECATED>
27 compatible = "snps,dw-apb-timer";
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| /Documentation/devicetree/bindings/serial/ |
| D | snps-dw-apb-uart.yaml | 4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
34 - const: snps,dw-apb-uart
37 - brcm,bcm11351-dw-apb-uart
38 - brcm,bcm21664-dw-apb-uart
39 - const: snps,dw-apb-uart
40 - const: snps,dw-apb-uart
106 compatible = "snps,dw-apb-uart";
121 compatible = "snps,dw-apb-uart";
132 compatible = "snps,dw-apb-uart";
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| /Documentation/devicetree/bindings/gpio/ |
| D | snps-dwapb-gpio.txt | 1 * Synopsys DesignWare APB GPIO controller
4 - compatible : Should contain "snps,dw-apb-gpio"
13 - compatible : "snps,dw-apb-gpio-port"
41 compatible = "snps,dw-apb-gpio";
47 compatible = "snps,dw-apb-gpio-port";
59 compatible = "snps,dw-apb-gpio-port";
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| D | sgpio-aspeed.txt | 10 - Directly connected to APB bus and its shift clock is from APB bus clock
25 - clocks : A phandle to the APB clock for SGPM clock division
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| /Documentation/devicetree/bindings/clock/ |
| D | moxa,moxart-clock.txt | 7 MOXA ART SoCs allow to determine PLL output and APB frequencies
23 APB:
26 - compatible : Must be "moxa,moxart-apb-clock"
44 compatible = "moxa,moxart-apb-clock";
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| D | lpc1850-cgu.txt | 51 and APB peripheral blocks #0 and #2
56 9 BASE_APB1_CLK Base clock for APB peripheral block # 1
57 10 BASE_APB3_CLK Base clock for APB peripheral block # 3
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| /Documentation/devicetree/bindings/pci/ |
| D | kirin-pcie.txt | 13 - reg: Should contain rc_dbi, apb, phy, config registers location and length.
16 "apb": apb Ctrl register defined by Kirin;
17 "phy": apb PHY register defined by Kirin;
29 reg-names = "dbi","apb","phy", "config";
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| D | amlogic,meson-pcie.txt | 28 - reset-names: must contain "phy" "port" and "apb"
31 - "apb" Share APB reset
69 "apb";
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| D | rockchip-pcie-ep.txt | 7 - "apb-base"
52 reg-names = "apb-base", "mem-base";
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| /Documentation/devicetree/bindings/sound/ |
| D | sun4i-codec.txt | 19 - "apb": the parent APB clock for this controller
71 clock-names = "apb", "codec";
82 clock-names = "apb", "codec";
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| D | allwinner,sun4i-a10-spdif.yaml | 45 - const: apb
117 clock-names = "apb", "spdif";
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| D | allwinner,sun4i-a10-i2s.yaml | 41 - const: apb
127 clock-names = "apb", "mod";
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| /Documentation/devicetree/bindings/spi/ |
| D | snps,dw-apb-ssi.txt | 4 - compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or
5 "jaguar2", or "amazon,alpine-dw-apb-ssi"
30 compatible = "snps,dw-apb-ssi";
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | mediatek,smi-larb.txt | 17 - "apb" : Advanced Peripheral Bus clock, It's the clock for setting
35 clock-names = "apb", "smi";
46 clock-names = "apb", "smi";
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| D | mediatek,smi-common.txt | 29 - "apb" : Advanced Peripheral Bus clock, It's the clock for setting
47 clock-names = "apb", "smi";
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| /Documentation/devicetree/bindings/thermal/ |
| D | zx2967-thermal.txt | 10 "apb" for the apb clock.
22 clock-names = "topcrm", "apb";
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| /Documentation/devicetree/bindings/dma/ |
| D | nvidia,tegra20-apbdma.txt | 1 * NVIDIA Tegra APB DMA controller
17 documentation of the APB DMA channel control register REQ_SEL field.
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | dw_mipi_dsi.txt | 20 - "pclk" is the peripheral clock for either AHB and APB. (mandatory)
26 - reset-names: string reset name, must be "apb" if used. (optional)
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | rockchip-saradc.txt | 24 - reset-names: Must include the name "saradc-apb".
34 reset-names = "saradc-apb";
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| /Documentation/devicetree/bindings/display/rockchip/ |
| D | dw_mipi_dsi_rockchip.txt | 12 clock(ref) and APB clock(pclk). For RK3399, a phy config clock
23 - reset-names: string reset name, must be "apb".
39 reset-names = "apb";
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| /Documentation/devicetree/bindings/media/ |
| D | allwinner,sun4i-a10-ir.yaml | 45 - const: apb
72 clock-names = "apb", "ir";
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| /Documentation/devicetree/bindings/display/exynos/ |
| D | exynos_hdmi.txt | 38 a) hdmi_pclk: Gate of HDMI IP APB bus.
39 b) hdmi_i_pclk: Gate of HDMI-PHY IP APB bus.
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| /Documentation/devicetree/bindings/timer/ |
| D | rda,8810pl-timer.txt | 11 apb@20900000 {
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