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/Documentation/media/uapi/v4l/
Dmmap.rst24 Streaming is an I/O method where only pointers to buffers are exchanged
26 mapping is primarily intended to map buffers in device memory into the
30 drivers support streaming as well, allocating buffers in DMA-able main
33 A driver can support many sets of buffers. Each set is identified by a
38 To allocate device buffers applications call the
40 of buffers and buffer type, for example ``V4L2_BUF_TYPE_VIDEO_CAPTURE``.
41 This ioctl can also be used to change the number of buffers or to free
42 the allocated memory, provided none of the buffers are still mapped.
44 Before applications can access the buffers they must map them into their
46 location of the buffers in device memory can be determined with the
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Ddev-decoder.rst12 from the client to process these buffers.
50 the destination buffer queue; for decoders, the queue of buffers containing
51 decoded frames; for encoders, the queue of buffers containing an encoded
54 into ``CAPTURE`` buffers.
78 ``OUTPUT`` buffers must be queued by the client in decode order; for
79 encoders ``CAPTURE`` buffers must be returned by the encoder in decode order.
86 buffers must be queued by the client in display order; for decoders,
87 ``CAPTURE`` buffers must be returned by the decoder in display order.
110 the source buffer queue; for decoders, the queue of buffers containing
111 an encoded bytestream; for encoders, the queue of buffers containing raw
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Duserp.rst25 methods. Buffers (planes) are allocated by the application itself, and
32 No buffers (planes) are allocated beforehand, consequently they are not
33 indexed and cannot be queried like mapped buffers with the
57 :ref:`VIDIOC_QBUF <VIDIOC_QBUF>` ioctl. Although buffers are commonly
66 Filled or displayed buffers are dequeued with the
72 Applications must take care not to free buffers without dequeuing.
73 Firstly, the buffers remain locked for longer, wasting physical memory.
79 buffers, to start capturing and enter the read loop. Here the
82 and enqueue buffers, when enough buffers are stacked up output is
84 buffers it must wait until an empty buffer can be dequeued and reused.
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Dvidioc-reqbufs.rst43 Memory mapped buffers are located in device memory and must be allocated
45 space. User buffers are allocated by applications themselves, and this
47 to setup some internal structures. Similarly, DMABUF buffers are
52 To allocate device buffers applications initialize all fields of the
55 the desired number of buffers, ``memory`` must be set to the requested
58 allocate the requested number of buffers and it stores the actual number
61 number is also possible when the driver requires more buffers to
63 buffers, one displayed and one filled by the application.
69 buffers. Note that if any buffers are still mapped or exported via DMABUF,
73 If ``V4L2_BUF_CAP_SUPPORTS_ORPHANED_BUFS`` is set, then these buffers are
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Ddmabuf.rst16 The DMABUF framework provides a generic method for sharing buffers
25 exporting V4L2 buffers as DMABUF file descriptors.
31 importing DMA buffers through DMABUF file descriptors is supported is
35 This I/O method is dedicated to sharing DMA buffers between different
37 DRM). Buffers (planes) are allocated by a driver on behalf of an
38 application. Next, these buffers are exported to the application as file
70 buffers, every plane can be associated with a different DMABUF
71 descriptor. Although buffers are commonly cycled, applications can pass
128 Captured or displayed buffers are dequeued with the
136 buffers, to start capturing and enter the read loop. Here the
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Dvidioc-create-bufs.rst19 VIDIOC_CREATE_BUFS - Create buffers for Memory Mapped or User Pointer or DMA Buffer I/O
42 This ioctl is used to create buffers for :ref:`memory mapped <mmap>`
46 over buffers is required. This ioctl can be called multiple times to
47 create buffers of different sizes.
49 To allocate the device buffers applications must initialize the relevant
51 ``count`` field must be set to the number of requested buffers, the
55 The ``format`` field specifies the image format that the buffers must be
62 sizes (for multi-planar formats) will be used for the allocated buffers.
66 The buffers created by this ioctl will have as minimum size the size
76 will attempt to allocate up to the requested number of buffers and store
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Dcapture.c.rst58 struct buffer *buffers;
98 if (-1 == read(fd, buffers[0].start, buffers[0].length)) {
113 process_image(buffers[0].start, buffers[0].length);
139 process_image(buffers[buf.index].start, buf.bytesused);
167 if (buf.m.userptr == (unsigned long)buffers[i].start
168 && buf.length == buffers[i].length)
275 buf.m.userptr = (unsigned long)buffers[i].start;
276 buf.length = buffers[i].length;
294 free(buffers[0].start);
299 if (-1 == munmap(buffers[i].start, buffers[i].length))
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Dvidioc-streamon.rst49 Capture hardware is disabled and no input buffers are filled (if there
50 are any empty buffers in the incoming queue) until ``VIDIOC_STREAMON``
58 If ``VIDIOC_STREAMON`` fails then any already queued buffers will remain
62 in progress, unlocks any user pointer buffers locked in physical memory,
63 and it removes all buffers from the incoming and outgoing queues. That
70 If buffers have been queued with :ref:`VIDIOC_QBUF` and
72 ``VIDIOC_STREAMON``, then those queued buffers will also be removed from
84 but ``VIDIOC_STREAMOFF`` will return queued buffers to their starting
103 The buffer ``type`` is not supported, or no buffers have been
Dv4l2grab.c.rst74 struct buffer *buffers;
103 buffers = calloc(req.count, sizeof(*buffers));
113 buffers[n_buffers].length = buf.length;
114 buffers[n_buffers].start = v4l2_mmap(NULL, buf.length,
118 if (MAP_FAILED == buffers[n_buffers].start) {
163 fwrite(buffers[buf.index].start, buf.bytesused, 1, fout);
172 v4l2_munmap(buffers[i].start, buffers[i].length);
Dfunc-read.rst67 single or multiple buffers and discarding the oldest or newest frames
68 once the internal buffers are filled.
93 buffers, automatically advancing to the next free buffer. This allows
94 continuous capturing when the application can empty the buffers fast
95 enough. Again, the behavior when the driver runs out of free buffers
98 Applications can get and set the number of buffers used internally by
Dvidioc-qbuf.rst54 range from zero to the number of buffers allocated with
87 out to disk. Buffers remain locked until dequeued, until the
103 buffer then the result is undefined. Buffers remain locked until
119 It is not allowed to mix queuing requests with queuing buffers directly.
127 ``request_fd`` only for output buffers, not for capture buffers. Attempting
172 bounds, or no buffers have been allocated yet, or the ``userptr`` or
194 dequeued and no new buffers are expected to become available.
/Documentation/media/uapi/dvb/
Ddmx-reqbufs.rst45 Memory mapped buffers are located in device memory and must be allocated
47 space. User buffers are allocated by applications themselves, and this
49 to setup some internal structures. Similarly, DMABUF buffers are
54 To allocate device buffers applications initialize all fields of the
56 to the desired number of buffers, and ``size`` to the size of each
60 attempt to allocate the requested number of buffers and it stores the actual
62 number is also possible when the driver requires more buffers to
70 buffers, however this cannot succeed when any buffers are still mapped.
71 A ``count`` value of zero frees all buffers, after aborting or finishing
/Documentation/media/kapi/
Dv4l2-videobuf.rst21 and user space. It handles the allocation and management of buffers for
34 Not all video devices use the same kind of buffers. In fact, there are (at
37 - Buffers which are scattered in both the physical and (kernel) virtual
38 address spaces. (Almost) all user-space buffers are like this, but it
39 makes great sense to allocate kernel-space buffers this way as well when
44 - Buffers which are physically scattered, but which are virtually
45 contiguous; buffers allocated with vmalloc(), in other words. These
46 buffers are just as hard to use for DMA operations, but they can be
48 buffers are convenient.
50 - Buffers which are physically contiguous. Allocation of this kind of
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/Documentation/media/v4l-drivers/
Dcafe_ccic.rst37 buffers until the time comes to transfer data. If this option is set,
38 then worst-case-sized buffers will be allocated at module load time.
42 - dma_buf_size: The size of DMA buffers to allocate. Note that this
43 option is only consulted for load-time allocation; when buffers are
48 buffers. Normally, the driver tries to use three buffers; on faster
51 - min_buffers: The minimum number of streaming I/O buffers that the driver
56 - max_buffers: The maximum number of streaming I/O buffers; default is
/Documentation/gpu/
Dxen-front.rst9 Driver modes of operation in terms of display buffers used
13 :doc: Driver modes of operation in terms of display buffers used
15 Buffers allocated by the frontend driver
19 :doc: Buffers allocated by the frontend driver
21 Buffers allocated by the backend
25 :doc: Buffers allocated by the backend
/Documentation/filesystems/
Drelay.txt9 as a set of per-cpu kernel buffers ('channel buffers'), each
11 clients write into the channel buffers using efficient write
16 are associated with the channel buffers using the API described below.
18 The format of the data logged into the channel buffers is completely
33 sub-buffers. Messages are written to the first sub-buffer until it is
35 the next (if available). Messages are never split across sub-buffers.
57 read sub-buffers; thus in cases where read(2) is being used to drain
58 the channel buffers, special-purpose communication between kernel and
93 allowing both to convey the state of buffers (full, empty, amount of
95 consumes the read sub-buffers; thus in cases where read(2) is being
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/Documentation/media/uapi/mediactl/
Drequest-api.rst44 on the media pipeline, reconfigure it for the next frame, queue the buffers to
51 specific buffers. This allows user-space to schedule several tasks ("requests")
82 instead of being immediately applied, and buffers queued to a request do not
88 Once the configuration and buffers of the request are specified, it can be
95 output buffers, not for capture buffers. Attempting to add a capture buffer
100 buffers are processed. Media controller drivers do a best effort implementation
105 It is not allowed to mix queuing requests with directly queuing buffers:
122 once all its associated buffers are available for dequeuing and all the
125 dequeue its buffers: buffers that are available halfway through a request can
158 to queue many such buffers in advance. It can also take advantage of requests'
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/Documentation/driver-api/usb/
Ddma.rst12 though they still must provide DMA-ready buffers (see
18 - New calls enable DMA-aware drivers, letting them allocate dma buffers and
19 manage dma mappings for existing dma-ready buffers (see below).
88 Working with existing buffers
91 Existing buffers aren't usable for DMA without first being mapped into the
92 DMA address space of the device. However, most buffers passed to your
113 buffers, synchronizing their safe re-use. (If there's no re-use, then let
131 They cannot be used for setup_packet buffers in control requests.
/Documentation/x86/
Dmds.rst10 on internal buffers in Intel CPUs. The variants are:
21 buffers are partitioned between Hyper-Threads so cross thread forwarding is
25 MFBDS leaks Fill Buffer Entries. Fill buffers are used internally to manage
27 to a memory or I/O operation. Fill buffers can forward data to a load
31 be exploited under certain conditions. Fill buffers are shared between
74 thread case (SMT off): Force the CPU to clear the affected buffers.
78 the affected CPU buffers when the VERW instruction is executed.
104 hope that it might actually clear the buffers. The state is reflected
139 When transitioning from kernel to user space the CPU buffers are flushed
157 When a CPU goes idle and enters a C-State the CPU buffers need to be
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/Documentation/driver-api/iio/
Dindex.rst15 buffers
17 triggered-buffers
/Documentation/admin-guide/hw-vuln/
Dtsx_async_abort.rst7 data which is available in various CPU internal buffers by using asynchronous
39 data into temporary microarchitectural structures (buffers). The data in
40 those buffers can be forwarded to load operations as an optimization.
54 executed loads may read data from those internal buffers and pass it to dependent
58 Because the buffers are potentially shared between Hyper-Threads cross
63 which in turn potenitally leaks data stored in the buffers.
100 * - 'Vulnerable: Clear CPU buffers attempted, no microcode'
101 - The system tries to clear the buffers but the microcode might not support the operation.
102 * - 'Mitigation: Clear CPU buffers'
103 - The microcode has been updated to clear the buffers. TSX is still enabled.
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/Documentation/i2c/
Ddma-considerations.rst19 safe buffers always, because USB requires it.
32 buffers in kernel space are always DMA capable. Also, when the core emulates
33 SMBus transactions via I2C, the buffers for block transfers are DMA safe. Users
36 know their buffers are DMA safe. Users of i2c_transfer() must set the
64 reusing pre-allocated buffers), you are free to implement your own.
/Documentation/networking/
Diphase.txt79 5.1 Configuration of adapter buffers
81 1M. The RAM size decides the number of buffers and buffer size. The default
82 size and number of buffers are set as following:
97 RX_CNT = number of receive buffers in the range (1-128)
98 RX_SIZE = size of receive buffers in the range (48-64K)
99 TX_CNT = number of transmit buffers in the range (1-128)
100 TX_SIZE = size of transmit buffers in the range (48-64K)
104 transmit and receive buffers is less than or equal to the
/Documentation/driver-api/
Dxillybus.rst94 sized buffers (even though such buffers are used by Xillybus under the hood).
101 up the DMA buffers and character devices accordingly. As a result, a single
152 room in the buffers to store any of the data in the buffers.
221 * bufnum: The number of buffers allocated for this pipe. Always a power of two.
268 sides, the implementation relies on a set of DMA buffers which is allocated
271 FPGA, the Xillybus IP core writes it to one of the DMA buffers. When the
291 filled buffers being sent) and a latency held fairly low for tails of data.
294 partial DMA buffers is somewhat different, though. The user can tell the
295 driver to submit all data it has in the buffers to the FPGA, by issuing a
304 to lay around in the DMA buffers between read() and write() anyhow.
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Ddma-buf.rst4 The dma-buf subsystem provides the framework for sharing buffers for
17 Shared DMA Buffers
21 buffer sharing API, how to use it for exporting and using shared buffers.
24 either the 'exporter' of buffers, or the 'user' or 'importer' of buffers.
26 Say a driver A wants to use buffers created by driver B, then we call B as the
71 access to buffers, via the leaked fd, to which it should otherwise

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