Searched +full:clock +full:- +full:output +full:- +full:names (Results 1 – 25 of 269) sorted by relevance
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| /Documentation/devicetree/bindings/clock/ |
| D | clock-bindings.txt | 1 This binding is a work-in-progress, and are based on some experimental
4 Sources of clock signal can be represented by any node in the device
5 tree. Those nodes are designated as clock providers. Clock consumer
6 nodes use a phandle and clock specifier pair to connect clock provider
7 outputs to clock inputs. Similar to the gpio specifiers, a clock
8 specifier is an array of zero, one or more cells identifying the clock
9 output on a device. The length of a clock specifier is defined by the
10 value of a #clock-cells property in the clock provider node.
14 ==Clock providers==
17 #clock-cells: Number of cells in a clock specifier; Typically 0 for nodes
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| D | xgene.txt | 1 Device Tree Clock bindings for APM X-Gene
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
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| D | imx8mn-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/bindings/clock/imx8mn-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8M Nano Clock Control Module Binding
10 - Anson Huang <Anson.Huang@nxp.com>
13 NXP i.MX8M Nano clock control module is an integrated clock controller, which
18 const: fsl,imx8mn-ccm
25 - description: 32k osc
26 - description: 24m osc
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| D | nuvoton,npcm750-clk.txt | 1 * Nuvoton NPCM7XX Clock Controller
3 Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
10 clk_sysbypck are inputs to the clock controller.
12 network. They are set on the device tree, but not used by the clock module. The
17 dt-bindings/clock/nuvoton,npcm7xx-clock.h
20 Required Properties of clock controller:
22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
25 - reg: physical base address of the clock controller and length of
28 - #clock-cells: should be 1.
30 Example: Clock controller node:
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| D | lpc1850-cgu.txt | 1 * NXP LPC1850 Clock Generation Unit (CGU)
4 peripheral blocks of the LPC18xx. Each independent clock is called
5 a base clock and itself is one of the inputs to the two Clock
9 The CGU selects the inputs to the clock generators from multiple
10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock source bus to the output
12 stages. Each output stage provides an independent clock source and
15 - Above text taken from NXP LPC1850 User Manual.
18 This binding uses the common clock binding:
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
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| D | keystone-pll.txt | 1 Status: Unstable - ABI compatibility may be broken in the future
9 This binding uses the common clock binding[1].
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
14 - #clock-cells : from common clock binding; shall be set to 0.
15 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
16 - clocks : parent clock phandle
17 - reg - pll control0 and pll multipler registers
18 - reg-names : control, multiplier and post-divider. The multiplier and
19 post-divider registers are applicable only for main pll clock
20 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
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| D | maxim,max9485.txt | 1 Devicetree bindings for Maxim MAX9485 Programmable Audio Clock Generator
5 - MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
6 - MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete
8 - MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT
14 - compatible: "maxim,max9485"
15 - clocks: Input clock, must provice 27.000 MHz
16 - clock-names: Must be set to "xclk"
17 - #clock-cells: From common clock binding; shall be set to 1
20 - reset-gpios: GPIO descriptor connected to the #RESET input pin
21 - vdd-supply: A regulator node for Vdd
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| D | sunxi.txt | 1 Device Tree Clock bindings for arch-sunxi
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
10 "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
11 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
12 "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
13 "allwinner,sun4i-a10-pll3-clk" - for the video PLL clock on A10
14 "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
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| D | keystone-gate.txt | 1 Status: Unstable - ABI compatibility may be broken in the future
5 This binding uses the common clock binding[1].
7 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
10 - compatible : shall be "ti,keystone,psc-clock".
11 - #clock-cells : from common clock binding; shall be set to 0.
12 - clocks : parent clock phandle
13 - reg : psc control and domain address address space
14 - reg-names : psc control and domain registers
15 - domain-id : psc domain id needed to check the transition state register
18 - clock-output-names : From common clock binding to override the
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| D | nvidia,tegra124-dfll.txt | 3 This binding uses the common clock binding:
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 the fast CPU cluster. It consists of a free-running voltage controlled
10 communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
13 - compatible : should be one of:
14 - "nvidia,tegra124-dfll": for Tegra124
15 - "nvidia,tegra210-dfll": for Tegra210
16 - reg : Defines the following set of registers, in the order listed:
17 - registers for the DFLL control logic.
18 - registers for the I2C output logic.
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| D | qcom,hfpll.txt | 1 High-Frequency PLL (HFPLL)
5 - compatible:
11 "qcom,hfpll-ipq8064", "qcom,hfpll"
12 "qcom,hfpll-apq8064", "qcom,hfpll"
13 "qcom,hfpll-msm8974", "qcom,hfpll"
14 "qcom,hfpll-msm8960", "qcom,hfpll"
16 - reg:
18 Value type: <prop-encoded-array>
23 - clocks:
25 Value type: <prop-encoded-array>
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| D | armada3700-xtal-clock.txt | 1 * Xtal Clock bindings for Marvell Armada 37xx SoCs
3 Marvell Armada 37xx SoCs allow to determine the xtal clock frequencies by
8 See Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
11 - compatible : shall be one of the following:
12 "marvell,armada-3700-xtal-clock"
13 - #clock-cells : from common clock binding; shall be set to 0
16 - clock-output-names : from common clock binding; allows overwrite default clock
17 output names ("xtal")
20 pinctrl_nb: pinctrl-nb@13800 {
21 compatible = "armada3710-nb-pinctrl", "syscon", "simple-mfd";
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| D | qoriq-clock.txt | 1 * Clock Block on Freescale QorIQ Platforms
14 --------------- -------------
18 1. Clock Block Binding
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
28 * "fsl,p4080-clockgen"
29 * "fsl,p5020-clockgen"
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| /Documentation/devicetree/bindings/phy/ |
| D | ti,phy-am654-serdes.txt | 4 - compatible: Should be "ti,phy-am654-serdes"
5 - reg : Address and length of the register set for the device.
6 - #phy-cells: determine the number of cells that should be given in the
9 include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes
12 0 - USB3
13 1 - PCIe0 Lane0
14 2 - ICSS2 SGMII Lane0
16 0 - PCIe1 Lane0
17 1 - PCIe0 Lane1
18 2 - ICSS2 SGMII Lane1
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| D | phy-rockchip-inno-hdmi.txt | 4 - compatible : should be one of the listed compatibles:
5 * "rockchip,rk3228-hdmi-phy",
6 * "rockchip,rk3328-hdmi-phy";
7 - reg : Address and length of the hdmi phy control register set
8 - clocks : phandle + clock specifier for the phy clocks
9 - clock-names : string, clock name, must contain "sysclk" for system
10 control and register configuration, "refoclk" for crystal-
11 oscillator reference PLL clock input and "refpclk" for pclk-
12 based refeference PLL clock input.
13 - #clock-cells: should be 0.
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| D | phy-rockchip-inno-usb2.txt | 4 - compatible : should be one of the listed compatibles:
5 * "rockchip,rk3228-usb2phy"
6 * "rockchip,rk3328-usb2phy"
7 * "rockchip,rk3366-usb2phy"
8 * "rockchip,rk3399-usb2phy"
9 * "rockchip,rv1108-usb2phy"
10 - reg : the address offset of grf for usb-phy configuration.
11 - #clock-cells : should be 0.
12 - clock-output-names : specify the 480m output clock name.
15 - clocks : phandle + phy specifier pair, for the input clock of phy.
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| /Documentation/devicetree/bindings/rtc/ |
| D | allwinner,sun6i-a31-rtc.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/rtc/allwinner,sun6i-a31-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <maxime.ripard@bootlin.com>
14 "#clock-cells":
19 - const: allwinner,sun6i-a31-rtc
20 - const: allwinner,sun8i-a23-rtc
21 - const: allwinner,sun8i-h3-rtc
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| /Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,dsi.txt | 5 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
6 channel output.
9 - compatible: "mediatek,<chip>-dsi"
11 - reg: Physical base address and length of the controller's registers
12 - interrupts: The interrupt signal from the function block.
13 - clocks: device clocks
14 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
15 - clock-names: must contain "engine", "digital", and "hs"
16 - phys: phandle link to the MIPI D-PHY controller.
17 - phy-names: must contain "dphy"
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| D | mediatek,hdmi.txt | 8 - compatible: Should be "mediatek,<chip>-hdmi".
9 - reg: Physical base address and length of the controller's registers
10 - interrupts: The interrupt signal from the function block.
11 - clocks: device clocks
12 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
13 - clock-names: must contain "pixel", "pll", "bclk", and "spdif".
14 - phys: phandle link to the HDMI PHY node.
15 See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
16 - phy-names: must contain "hdmi"
17 - mediatek,syscon-hdmi: phandle link and register offset to the system
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| /Documentation/devicetree/bindings/mfd/ |
| D | ac100.txt | 1 X-Powers AC100 Codec/RTC IC Device Tree bindings
8 - compatible: "x-powers,ac100"
9 - reg: The I2C slave address or RSB hardware address for the chip
10 - sub-nodes:
11 - codec
12 - compatible: "x-powers,ac100-codec"
13 - interrupts: SoC NMI / GPIO interrupt connected to the
15 - #clock-cells: Shall be 0
16 - clock-output-names: "4M_adda"
18 - see clock/clock-bindings.txt for common clock bindings
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| /Documentation/devicetree/bindings/display/ |
| D | arm,malidp.txt | 1 ARM Mali-DP
6 rotation and scaling output.
9 - compatible: should be one of
10 "arm,mali-dp500"
11 "arm,mali-dp550"
12 "arm,mali-dp650"
14 - reg: Physical base address and size of the block of registers used by
16 - interrupts: Interrupt list, as defined in ../interrupt-controller/interrupts.txt,
18 - interrupt-names: name of the engine inside the processor that will
20 - clocks: A list of phandle + clock-specifier pairs, one for each entry
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| D | st,stm32-ltdc.txt | 1 * STMicroelectronics STM32 lcd-tft display controller
3 - ltdc: lcd-tft display controller host
5 - compatible: "st,stm32-ltdc"
6 - reg: Physical base address of the IP registers and length of memory mapped region.
7 - clocks: A list of phandle + clock-specifier pairs, one for each
8 entry in 'clock-names'.
9 - clock-names: A list of clock names. For ltdc it should contain:
10 - "lcd" for the clock feeding the output pixel clock & IP clock.
11 - resets: reset to be used by the device (defined by use of RCC macro).
13 - Video port for DPI RGB output: ltdc has one video port with up to 2
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| /Documentation/devicetree/bindings/arm/ |
| D | sp810.txt | 2 -----------------------
6 - compatible: standard compatible string for a Primecell peripheral,
11 - reg: standard registers property, physical address and size
14 - clock-names: from the common clock bindings, for more details see
15 Documentation/devicetree/bindings/clock/clock-bindings.txt;
18 - clocks: from the common clock bindings, phandle and clock
19 specifier pairs for the entries of clock-names property
21 - #clock-cells: from the common clock bindings;
24 - clock-output-names: from the common clock bindings;
27 - assigned-clocks: from the common clock binding;
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| /Documentation/devicetree/bindings/arm/msm/ |
| D | qcom,kpss-gcc.txt | 1 Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
5 - compatible:
9 "qcom,kpss-gcc" should also be included.
10 "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"
11 "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc"
12 "qcom,kpss-gcc-msm8974", "qcom,kpss-gcc"
13 "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc"
15 - reg:
17 Value type: <prop-encoded-array>
20 - clocks:
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| D | qcom,kpss-acc.txt | 1 Krait Processor Sub-system (KPSS) Application Clock Controller (ACC)
3 The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
10 - compatible:
14 "qcom,kpss-acc-v1"
15 "qcom,kpss-acc-v2"
17 - reg:
19 Value type: <prop-encoded-array>
24 - clocks:
26 Value type: <prop-encoded-array>
29 - clock-names:
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