1* STMicroelectronics STM32 lcd-tft display controller 2 3- ltdc: lcd-tft display controller host 4 Required properties: 5 - compatible: "st,stm32-ltdc" 6 - reg: Physical base address of the IP registers and length of memory mapped region. 7 - clocks: A list of phandle + clock-specifier pairs, one for each 8 entry in 'clock-names'. 9 - clock-names: A list of clock names. For ltdc it should contain: 10 - "lcd" for the clock feeding the output pixel clock & IP clock. 11 - resets: reset to be used by the device (defined by use of RCC macro). 12 Required nodes: 13 - Video port for DPI RGB output: ltdc has one video port with up to 2 14 endpoints: 15 - for external dpi rgb panel or bridge, using gpios. 16 - for internal dpi input of the MIPI DSI host controller. 17 Note: These 2 endpoints cannot be activated simultaneously. 18 19* STMicroelectronics STM32 DSI controller specific extensions to Synopsys 20 DesignWare MIPI DSI host controller 21 22The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI 23DSI host controller. For all mandatory properties & nodes, please refer 24to the related documentation in [5]. 25 26Mandatory properties specific to STM32 DSI: 27- #address-cells: Should be <1>. 28- #size-cells: Should be <0>. 29- compatible: "st,stm32-dsi". 30- clock-names: 31 - phy pll reference clock string name, must be "ref". 32- resets: see [5]. 33- reset-names: see [5]. 34 35Mandatory nodes specific to STM32 DSI: 36- ports: A node containing DSI input & output port nodes with endpoint 37 definitions as documented in [3] & [4]. 38 - port@0: DSI input port node, connected to the ltdc rgb output port. 39 - port@1: DSI output port node, connected to a panel or a bridge input port. 40- panel or bridge node: A node containing the panel or bridge description as 41 documented in [6]. 42 - port: panel or bridge port node, connected to the DSI output port (port@1). 43Optional properties: 44- phy-dsi-supply: phandle of the regulator that provides the supply voltage. 45 46Note: You can find more documentation in the following references 47[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 48[2] Documentation/devicetree/bindings/reset/reset.txt 49[3] Documentation/devicetree/bindings/media/video-interfaces.txt 50[4] Documentation/devicetree/bindings/graph.txt 51[5] Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt 52[6] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt 53 54Example 1: RGB panel 55/ { 56 ... 57 soc { 58 ... 59 ltdc: display-controller@40016800 { 60 compatible = "st,stm32-ltdc"; 61 reg = <0x40016800 0x200>; 62 interrupts = <88>, <89>; 63 resets = <&rcc STM32F4_APB2_RESET(LTDC)>; 64 clocks = <&rcc 1 CLK_LCD>; 65 clock-names = "lcd"; 66 67 port { 68 ltdc_out_rgb: endpoint { 69 }; 70 }; 71 }; 72 }; 73}; 74 75Example 2: DSI panel 76 77/ { 78 ... 79 soc { 80 ... 81 ltdc: display-controller@40016800 { 82 compatible = "st,stm32-ltdc"; 83 reg = <0x40016800 0x200>; 84 interrupts = <88>, <89>; 85 resets = <&rcc STM32F4_APB2_RESET(LTDC)>; 86 clocks = <&rcc 1 CLK_LCD>; 87 clock-names = "lcd"; 88 89 port { 90 ltdc_out_dsi: endpoint { 91 remote-endpoint = <&dsi_in>; 92 }; 93 }; 94 }; 95 96 97 dsi: dsi@40016c00 { 98 #address-cells = <1>; 99 #size-cells = <0>; 100 compatible = "st,stm32-dsi"; 101 reg = <0x40016c00 0x800>; 102 clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>; 103 clock-names = "pclk", "ref"; 104 resets = <&rcc STM32F4_APB2_RESET(DSI)>; 105 reset-names = "apb"; 106 phy-dsi-supply = <®18>; 107 108 ports { 109 #address-cells = <1>; 110 #size-cells = <0>; 111 112 port@0 { 113 reg = <0>; 114 dsi_in: endpoint { 115 remote-endpoint = <<dc_out_dsi>; 116 }; 117 }; 118 119 port@1 { 120 reg = <1>; 121 dsi_out: endpoint { 122 remote-endpoint = <&dsi_in_panel>; 123 }; 124 }; 125 126 }; 127 128 panel-dsi@0 { 129 reg = <0>; /* dsi virtual channel (0..3) */ 130 compatible = ...; 131 enable-gpios = ...; 132 133 port { 134 dsi_in_panel: endpoint { 135 remote-endpoint = <&dsi_out>; 136 }; 137 }; 138 139 }; 140 141 }; 142 143 }; 144}; 145