Searched +full:cs +full:- +full:gpios (Results 1 – 25 of 42) sorted by relevance
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| /Documentation/devicetree/bindings/spi/ |
| D | brcm,bcm2835-aux-spi.txt | 8 - compatible: Should be "brcm,bcm2835-aux-spi".
9 - reg: Should contain register location and length for the spi block
10 - interrupts: Should contain shared interrupt of the aux block
11 - clocks: The clock feeding the SPI controller - needs to
15 - cs-gpios: the cs-gpios (native cs is NOT supported)
16 see also spi-bus.txt
21 compatible = "brcm,bcm2835-aux-spi";
25 #address-cells = <1>;
26 #size-cells = <0>;
27 cs-gpios = <&gpio 18>, <&gpio 17>, <&gpio 16>;
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| D | spi-dw.txt | 4 - compatible: should be "snps,designware-spi"
5 - #address-cells: see spi-bus.txt
6 - #size-cells: see spi-bus.txt
7 - reg: address and length of the spi master registers
8 - interrupts: should contain one interrupt
9 - clocks: spi clock phandle
10 - num-cs: see spi-bus.txt
13 - cs-gpios: see spi-bus.txt
18 compatible = "snps,designware-spi";
22 num-cs = <2>;
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| D | spi-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
20 pattern: "^spi(@.*|-[0-9a-f])*$"
22 "#address-cells":
25 "#size-cells":
28 cs-gpios:
30 GPIOs used as chip selects.
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| D | spi-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-GPIO devicetree bindings
10 - Rob Herring <robh@kernel.org>
13 This represents a group of 3-n GPIO lines used for bit-banged SPI on
17 - $ref: "/schemas/spi/spi-controller.yaml#"
21 const: spi-gpio
23 sck-gpios:
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| D | snps,dw-apb-ssi.txt | 4 - compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or
5 "jaguar2", or "amazon,alpine-dw-apb-ssi"
6 - reg : The register base for the controller. For "mscc,<soc>-spi", a second
8 - interrupts : One interrupt, used by the controller.
9 - #address-cells : <1>, as required by generic SPI binding.
10 - #size-cells : <0>, also as required by generic SPI binding.
11 - clocks : phandles for the clocks, see the description of clock-names below.
13 is optional. If a single clock is specified but no clock-name, it is the
17 - clock-names : Contains the names of the clocks:
20 - cs-gpios : Specifies the gpio pins to be used for chipselects.
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| D | spi_atmel.txt | 4 - compatible : should be "atmel,at91rm9200-spi".
5 - reg: Address and length of the register set for the device
6 - interrupts: Should contain spi interrupt
7 - cs-gpios: chipselects (optional for SPI controller version >= 2 with the
9 - clock-names: tuple listing input clock names.
11 - clocks: phandles to input clocks.
14 - atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO
20 compatible = "atmel,at91rm9200-spi";
23 #address-cells = <1>;
24 #size-cells = <0>;
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| D | spi-samsung.txt | 8 - compatible: should be one of the following.
9 - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms
10 - samsung,s3c6410-spi: for s3c6410 platforms
11 - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
12 - samsung,exynos5433-spi: for exynos5433 compatible controllers
13 - samsung,exynos7-spi: for exynos7 platforms <DEPRECATED>
15 - reg: physical base address of the controller and length of memory mapped
18 - interrupts: The interrupt number to the cpu. The interrupt specifier format
21 - dmas : Two or more DMA channel specifiers following the convention outlined
24 - dma-names: Names for the dma channels. There must be at least one channel
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| D | fsl-imx-cspi.txt | 5 - compatible :
6 - "fsl,imx1-cspi" for SPI compatible with the one integrated on i.MX1
7 - "fsl,imx21-cspi" for SPI compatible with the one integrated on i.MX21
8 - "fsl,imx27-cspi" for SPI compatible with the one integrated on i.MX27
9 - "fsl,imx31-cspi" for SPI compatible with the one integrated on i.MX31
10 - "fsl,imx35-cspi" for SPI compatible with the one integrated on i.MX35
11 - "fsl,imx51-ecspi" for SPI compatible with the one integrated on i.MX51
12 - "fsl,imx53-ecspi" for SPI compatible with the one integrated on i.MX53 and later Soc
13 - "fsl,imx8mq-ecspi" for SPI compatible with the one integrated on i.MX8M
14 - reg : Offset and length of the register set for the device
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| D | efm32-spi.txt | 4 - #address-cells: see spi-bus.txt
5 - #size-cells: see spi-bus.txt
6 - compatible: should be "energymicro,efm32-spi"
7 - reg: Offset and length of the register set for the controller
8 - interrupts: pair specifying rx and tx irq
9 - clocks: phandle to the spi clock
10 - cs-gpios: see spi-bus.txt
13 - energymicro,location: Value to write to the ROUTE register's LOCATION
23 #address-cells = <1>;
24 #size-cells = <0>;
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| D | spi-davinci.txt | 4 Keystone 2 - http://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
5 dm644x - http://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
9 - #address-cells: number of cells required to define a chip select
11 - #size-cells: should be zero.
12 - compatible:
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
15 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
17 - reg: Offset and length of SPI controller register space
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| D | spi-st-ssc.txt | 2 ---------------------------------------
5 - compatible : "st,comms-ssc4-spi"
6 - reg : Offset and length of the device's register set
7 - interrupts : The interrupt specifier
8 - clock-names : Must contain "ssc"
9 - clocks : Must contain an entry for each name in clock-names
11 - pinctrl-names : Uses "default", can use "sleep" if provided
12 See ../pinctrl/pinctrl-bindings.txt
15 - cs-gpios : List of GPIO chip selects
16 See ../spi/spi-bus.txt
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| D | microchip,spi-pic32.txt | 4 - compatible: Should be "microchip,pic32mzda-spi".
5 - reg: Address and length of register space for the device.
6 - interrupts: Should contain all three spi interrupts in sequence
7 of <fault-irq>, <receive-irq>, <transmit-irq>.
8 - interrupt-names: Should be "fault", "rx", "tx" in order.
9 - clocks: Phandle of the clock generating SPI clock on the bus.
10 - clock-names: Should be "mck0".
11 - cs-gpios: Specifies the gpio pins to be used for chipselects.
12 See: Documentation/devicetree/bindings/spi/spi-bus.txt
15 - dmas: Two or more DMA channel specifiers following the convention outlined
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| D | nuvoton,npcm-pspi.txt | 6 - compatible : "nuvoton,npcm750-pspi" for NPCM7XX BMC
7 - #address-cells : should be 1. see spi-bus.txt
8 - #size-cells : should be 0. see spi-bus.txt
9 - specifies physical base address and size of the register.
10 - interrupts : contain PSPI interrupt.
11 - clocks : phandle of PSPI reference clock.
12 - clock-names: Should be "clk_apb5".
13 - pinctrl-names : a pinctrl state named "default" must be defined.
14 - pinctrl-0 : phandle referencing pin configuration of the device.
15 - cs-gpios: Specifies the gpio pins to be used for chipselects.
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| D | spi-mt65xx.txt | 4 - compatible: should be one of the following.
5 - mediatek,mt2701-spi: for mt2701 platforms
6 - mediatek,mt2712-spi: for mt2712 platforms
7 - mediatek,mt6589-spi: for mt6589 platforms
8 - mediatek,mt6765-spi: for mt6765 platforms
9 - mediatek,mt7622-spi: for mt7622 platforms
10 - "mediatek,mt7629-spi", "mediatek,mt7622-spi": for mt7629 platforms
11 - mediatek,mt8135-spi: for mt8135 platforms
12 - mediatek,mt8173-spi: for mt8173 platforms
13 - mediatek,mt8183-spi: for mt8183 platforms
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| D | qcom,spi-qup.txt | 4 and an input FIFO) for serial peripheral interface (SPI) mini-core.
10 - compatible: Should contain:
11 "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064.
12 "qcom,spi-qup-v2.1.1" for 8974 and later
13 "qcom,spi-qup-v2.2.1" for 8974 v2 and later.
15 - reg: Should contain base register location and length
16 - interrupts: Interrupt number used by this controller
18 - clocks: Should contain the core clock and the AHB clock.
19 - clock-names: Should be "core" for the core clock and "iface" for the
22 - #address-cells: Number of cells required to define a chip select
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| D | sh-msiof.txt | 4 - compatible : "renesas,msiof-r8a7743" (RZ/G1M)
5 "renesas,msiof-r8a7744" (RZ/G1N)
6 "renesas,msiof-r8a7745" (RZ/G1E)
7 "renesas,msiof-r8a77470" (RZ/G1C)
8 "renesas,msiof-r8a774a1" (RZ/G2M)
9 "renesas,msiof-r8a774c0" (RZ/G2E)
10 "renesas,msiof-r8a7790" (R-Car H2)
11 "renesas,msiof-r8a7791" (R-Car M2-W)
12 "renesas,msiof-r8a7792" (R-Car V2H)
13 "renesas,msiof-r8a7793" (R-Car M2-N)
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| D | spi-stm32.txt | 4 the Serial Peripheral Interface. It supports full-duplex, half-duplex and
6 from 4 to 32-bit data size. Although it can be configured as master or slave,
10 - compatible: Should be one of:
11 "st,stm32h7-spi"
12 "st,stm32f4-spi"
13 - reg: Offset and length of the device's register set.
14 - interrupts: Must contain the interrupt id.
15 - clocks: Must contain an entry for spiclk (which feeds the internal clock
17 - #address-cells: Number of cells required to define a chip select address.
18 - #size-cells: Should be zero.
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| D | spi-pxa2xx.txt | 4 - compatible: Must be "marvell,mmp2-ssp".
5 - reg: Offset and length of the device's register set.
6 - interrupts: Should be the interrupt number.
7 - clocks: Should contain a single entry describing the clock input.
8 - #address-cells: Number of cells required to define a chip select address.
9 - #size-cells: Should be zero.
12 - cs-gpios: list of GPIO chip selects. See the SPI bus bindings,
13 Documentation/devicetree/bindings/spi/spi-bus.txt
14 - spi-slave: Empty property indicating the SPI controller is used in slave mode.
15 - ready-gpios: GPIO used to signal a SPI master that the FIFO is filled
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| /Documentation/devicetree/bindings/gpio/ |
| D | spear_spics.txt | 1 === ST Microelectronics SPEAr SPI CS Driver ===
10 Chipselects can be controlled by software by turning them as GPIOs. SPEAr
17 * compatible: should be defined as "st,spear-spics-gpio"
19 * st-spics,peripcfg-reg: peripheral configuration register offset
20 * st-spics,sw-enable-bit: bit offset to enable sw control
21 * st-spics,cs-value-bit: bit offset to drive chipselect low or high
22 * st-spics,cs-enable-mask: chip select number bit mask
23 * st-spics,cs-enable-shift: chip select number program offset
24 * gpio-controller: Marks the device node as gpio controller
25 * #gpio-cells: should be 1 and will mention chip select number
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| /Documentation/devicetree/bindings/mfd/ |
| D | atmel-usart.txt | 4 - compatible: Should be "atmel,<chip>-usart" or "atmel,<chip>-dbgu"
7 For the dbgu UART, use "atmel,<chip>-dbgu", "atmel,<chip>-usart"
8 - reg: Should contain registers location and length
9 - interrupts: Should contain interrupt
10 - clock-names: tuple listing input clock names.
12 - clocks: phandles to input clocks.
15 - #size-cells : Must be <0>
16 - #address-cells : Must be <1>
17 - cs-gpios: chipselects (internal cs not supported)
18 - atmel,usart-mode : Must be <AT91_USART_MODE_SPI> (found in dt-bindings/mfd/at91-usart.h)
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| /Documentation/devicetree/bindings/mtd/ |
| D | fsl-upm-nand.txt | 4 - compatible : "fsl,upm-nand".
5 - reg : should specify localbus chip select and size used for the chip.
6 - fsl,upm-addr-offset : UPM pattern offset for the address latch.
7 - fsl,upm-cmd-offset : UPM pattern offset for the command latch.
10 - fsl,upm-wait-flags : add chip-dependent short delays after running the
13 - fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
15 - gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins
16 (R/B#). For multi-chip devices, "n" GPIO definitions are required
18 - chip-delay : chip dependent delay for transferring data from array to
19 read registers (tR). Required if property "gpios" is not used
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| D | gpmc-onenand.txt | 7 explained in a separate documents - please refer to
8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
12 - compatible: "ti,omap2-onenand"
13 - reg: The CS line the peripheral is connected to
14 - gpmc,device-width: Width of the ONENAND device connected to the GPMC
19 - int-gpios: GPIO specifier for the INT pin.
23 - #address-cells: should be set to 1
24 - #size-cells: should be set to 1
29 compatible = "ti,omap3430-gpmc";
33 gpmc,num-cs = <8>;
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| D | atmel-nand.txt | 4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
17 "microchip,sam9x60-nand-controller"
18 - ranges: empty ranges property to forward EBI ranges definitions.
19 - #address-cells: should be set to 2.
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| /Documentation/devicetree/bindings/misc/ |
| D | eeprom-93xx46.txt | 4 - compatible : shall be one of:
6 "eeprom-93xx46"
7 - data-size : number of data bits per word (either 8 or 16)
10 - read-only : parameter-less property which disables writes to the EEPROM
11 - select-gpios : if present, specifies the GPIO that will be asserted prior to
14 Property rules described in Documentation/devicetree/bindings/spi/spi-bus.txt
15 apply. In particular, "reg" and "spi-max-frequency" properties must be given.
19 compatible = "eeprom-93xx46";
21 spi-max-frequency = <1000000>;
22 spi-cs-high;
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| /Documentation/devicetree/bindings/display/panel/ |
| D | kingdisplay,kd035g6-54nt.txt | 1 King Display KD035G6-54NT 3.5" (320x240 pixels) 24-bit TFT LCD panel
4 - compatible: should be "kingdisplay,kd035g6-54nt"
5 - power-supply: See panel-common.txt
6 - reset-gpios: See panel-common.txt
9 - backlight: see panel-common.txt
17 [1]: Documentation/devicetree/bindings/spi/spi-bus.txt
24 compatible = "kingdisplay,kd035g6-54nt";
27 spi-max-frequency = <3125000>;
28 spi-3wire;
29 spi-cs-high;
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