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/Documentation/devicetree/bindings/i2c/
Di2c-mux-pinctrl.txt1 Pinctrl-based I2C Bus Mux
3 This binding describes an I2C bus multiplexer that uses pin multiplexing to
4 route the I2C signals, and represents the pin multiplexing configuration
7 +-----+ +-----+
9 +------------------------+ +-----+ +-----+
11 | /----|------+--------+
12 | +---+ +------+ | child bus A, on first set of pins
13 | |I2C|---|Pinmux| |
14 | +---+ +------+ | child bus B, on second set of pins
15 | \----|------+--------+--------+
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Di2c-stu300.txt1 ST Microelectronics DDC I2C
4 - compatible : Must be "st,ddci2c"
5 - reg: physical base address of the controller and length of memory mapped
7 - interrupts: interrupt number to the cpu.
8 - #address-cells = <1>;
9 - #size-cells = <0>;
12 - Child nodes conforming to i2c bus binding
/Documentation/devicetree/bindings/display/connector/
Dvga-connector.txt6 - compatible: "vga-connector"
10 - label: a symbolic name for the connector corresponding to a hardware label
11 - ddc-i2c-bus: phandle to the I2C bus that is connected to VGA DDC
23 -------
26 compatible = "vga-connector";
29 ddc-i2c-bus = <&i2c3>;
33 remote-endpoint = <&adv7123_out>;
Dhdmi-connector.txt5 - compatible: "hdmi-connector"
6 - type: the HDMI connector type: "a", "b", "c", "d" or "e"
9 - label: a symbolic name for the connector
10 - hpd-gpios: HPD GPIO number
11 - ddc-i2c-bus: phandle link to the I2C controller used for DDC EDID probing
12 - ddc-en-gpios: signal to enable DDC bus
15 - Video port for HDMI input
18 -------
21 compatible = "hdmi-connector";
28 remote-endpoint = <&tpd12s015_out>;
Ddvi-connector.txt5 - compatible: "dvi-connector"
8 - label: a symbolic name for the connector
9 - ddc-i2c-bus: phandle to the i2c bus that is connected to DVI DDC
10 - analog: the connector has DVI analog pins
11 - digital: the connector has DVI digital pins
12 - dual-link: the connector has pins for DVI dual-link
13 - hpd-gpios: HPD GPIO number
16 - Video port for DVI input
21 -------
24 compatible = "dvi-connector";
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/Documentation/devicetree/bindings/display/imx/
Dhdmi.txt9 following device-specific properties.
14 - compatible : Shall be one of "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
15 - reg: See dw_hdmi.txt.
16 - interrupts: HDMI interrupt number
17 - clocks: See dw_hdmi.txt.
18 - clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
19 - ports: See dw_hdmi.txt. The DWC HDMI shall have between one and four ports,
22 - gpr : Shall contain a phandle to the iomuxc-gpr region containing the HDMI
27 - ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
28 or the functionally-reduced I2C master contained in the DWC HDMI. When
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Dldb.txt1 Device-Tree bindings for LVDS Display Bridge (ldb)
6 The LVDS Display Bridge device tree node contains up to two lvds-channel
10 - #address-cells : should be <1>
11 - #size-cells : should be <0>
12 - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb".
16 - gpr : should be <&gpr> on i.MX53 and i.MX6q.
17 The phandle points to the iomuxc-gpr region containing the LVDS
19 - clocks, clock-names : phandles to the LDB divider and selector clocks and to
21 Documentation/devicetree/bindings/clock/clock-bindings.txt
23 "di0_pll" - LDB LVDS channel 0 mux
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Dfsl-imx-drm.txt8 - compatible: Should be "fsl,imx-display-subsystem"
9 - ports: Should contain a list of phandles pointing to display interface ports
14 display-subsystem {
15 compatible = "fsl,display-subsystem";
24 - compatible: Should be "fsl,<chip>-ipu" where <chip> is one of
25 - imx51
26 - imx53
27 - imx6q
28 - imx6qp
29 - reg: should be register base and length as documented in the
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/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,hdmi.txt8 - compatible: Should be "mediatek,<chip>-hdmi".
9 - reg: Physical base address and length of the controller's registers
10 - interrupts: The interrupt signal from the function block.
11 - clocks: device clocks
12 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
13 - clock-names: must contain "pixel", "pll", "bclk", and "spdif".
14 - phys: phandle link to the HDMI PHY node.
15 See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
16 - phy-names: must contain "hdmi"
17 - mediatek,syscon-hdmi: phandle link and register offset to the system
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/Documentation/devicetree/bindings/display/rockchip/
Ddw_hdmi-rockchip.txt9 following device-specific properties.
14 - compatible: should be one of the following:
15 "rockchip,rk3228-dw-hdmi"
16 "rockchip,rk3288-dw-hdmi"
17 "rockchip,rk3328-dw-hdmi"
18 "rockchip,rk3399-dw-hdmi"
19 - reg: See dw_hdmi.txt.
20 - reg-io-width: See dw_hdmi.txt. Shall be 4.
21 - interrupts: HDMI interrupt number
22 - clocks: See dw_hdmi.txt.
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/Documentation/devicetree/bindings/display/panel/
Dpanel-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
24 width-mm:
29 height-mm:
43 non-descriptive information. For instance an LCD panel in a system that
52 - $ref: /schemas/types.yaml#/definitions/uint32
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/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra20-host1x.txt4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
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/Documentation/misc-devices/
Deeprom.rst11 Addresses scanned: I2C 0x50 - 0x57
28 24C01 1K 0x50 (shadows at 0x51 - 0x57)
29 24C01A 1K 0x50 - 0x57 (Typical device on DIMMs)
30 24C02 2K 0x50 - 0x57
35 24C16 16K 0x50 (additional data at 0x51 - 0x57)
38 Atmel 34C02B 2K 0x50 - 0x57, SW write protect at 0x30-37
39 Catalyst 34FC02 2K 0x50 - 0x57, SW write protect at 0x30-37
40 Catalyst 34RC02 2K 0x50 - 0x57, SW write protect at 0x30-37
41 Fairchild 34W02 2K 0x50 - 0x57, SW write protect at 0x30-37
42 Microchip 24AA52 2K 0x50 - 0x57, SW write protect at 0x30-37
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