| /Documentation/devicetree/bindings/net/dsa/ |
| D | dsa.txt | 2 ----------------------------------------------------
12 - ports : A container for child nodes representing switch ports.
16 - dsa,member : A two element list indicates which DSA cluster, and position
26 - #address-cells : Must be 1
27 - #size-cells : Must be 0
30 - reg : Describes the port address in the switch
35 - link : Should be a list of phandles to other switch's DSA
43 - ethernet : Should be a phandle to a valid Ethernet device node.
49 - label : Describes the label associated with this port, which
55 - phy-handle : Phandle to a PHY on an MDIO bus. See
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| D | qca8k.txt | 5 - compatible: should be one of:
9 - #size-cells: must be 0
10 - #address-cells: must be 1
14 - reset-gpios: GPIO to be used to reset the whole device
20 mdio-bus each subnode describing a port needs to have a valid phandle
24 Don't use mixed external and internal mdio-bus configurations, as this is
31 - fixed-link : Fixed-link subnode describing a link to a non-MDIO
33 Documentation/devicetree/bindings/net/fixed-link.txt
36 For QCA8K the 'fixed-link' sub-node supports only the following properties:
38 - 'speed' (integer, mandatory), to indicate the link speed. Accepted
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| D | lan9303.txt | 2 -------------------------------------------------
6 - compatible: should be
7 - "smsc,lan9303-i2c" for I2C managed mode
9 - "smsc,lan9303-mdio" for mdio managed mode
13 - reset-gpios: GPIO to be used to reset the whole device
14 - reset-duration: reset duration in milliseconds, defaults to 200 ms
23 auto-detected and mapped accordingly.
31 fixed-link { /* RMII fixed link to LAN9303 */
33 full-duplex;
38 compatible = "smsc,lan9303-i2c";
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| D | ksz.txt | 6 - compatible: For external switch chips, compatible string must be exactly one
8 - "microchip,ksz8765"
9 - "microchip,ksz8794"
10 - "microchip,ksz8795"
11 - "microchip,ksz9477"
12 - "microchip,ksz9897"
13 - "microchip,ksz9896"
14 - "microchip,ksz9567"
15 - "microchip,ksz8565"
16 - "microchip,ksz9893"
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| D | sja1105.txt | 6 - compatible:
8 - "nxp,sja1105e"
9 - "nxp,sja1105t"
10 - "nxp,sja1105p"
11 - "nxp,sja1105q"
12 - "nxp,sja1105r"
13 - "nxp,sja1105s"
18 and the non-SGMII devices, while pin-compatible, are not equal in terms
24 - sja1105,role-mac:
25 - sja1105,role-phy:
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| D | b53.txt | 6 - compatible: For external switch chips, compatible string must be exactly one
18 "brcm,bcm11360-srab" and the mandatory "brcm,cygnus-srab" string
21 "brcm,bcm53010-srab"
22 "brcm,bcm53011-srab"
23 "brcm,bcm53012-srab"
24 "brcm,bcm53018-srab"
25 "brcm,bcm53019-srab" and the mandatory "brcm,bcm5301x-srab" string
28 "brcm,bcm11404-srab"
29 "brcm,bcm11407-srab"
30 "brcm,bcm11409-srab"
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| D | mt7530.txt | 6 - compatible: may be compatible = "mediatek,mt7530"
8 - #address-cells: Must be 1.
9 - #size-cells: Must be 0.
10 - mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
11 on multi-chip module belong to MT7623A has or the remotely standalone
16 - core-supply: Phandle to the regulator node necessary for the core power.
17 - io-supply: Phandle to the regulator node necessary for the I/O power.
18 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
23 - reset-gpios: Should be a gpio specifier for a reset line.
27 - resets : Phandle pointing to the system reset controller with
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| D | vitesse,vsc73xx.txt | 9 Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
10 Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
11 Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
12 Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
17 reside inside a SPI bus device tree node, see spi/spi-bus.txt
19 When the chip is connected to a parallel memory bus and work in memory-mapped
25 - compatible: must be exactly one of:
30 - gpio-controller: indicates that this switch is also a GPIO controller,
32 - #gpio-cells: this must be set to <2> and indicates that we are a twocell
37 - reset-gpios: a handle to a GPIO line that can issue reset of the chip.
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| /Documentation/devicetree/bindings/net/ |
| D | fsl-enetc.txt | 4 external) there are two supported link modes specified by
9 - reg : Specifies PCIe Device Number and Function
12 - compatible : Should be "fsl,enetc".
18 In this case, the ENETC node should include a "mdio" sub-node
19 that in turn should contain the "ethernet-phy" node describing the
26 - phy-handle : Phandle to a PHY on the MDIO bus.
29 - phy-connection-type : Defined in ethernet.txt.
31 - mdio : "mdio" node, defined in mdio.txt.
33 - ethernet-phy : "ethernet-phy" node, defined in phy.txt.
40 phy-handle = <&sgmii_phy0>;
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| D | nixge.txt | 4 - compatible: Should be "ni,xge-enet-3.00", but can be "ni,xge-enet-2.00" for
5 older device trees with DMA engines co-located in the address map,
7 - reg: Address and length of the register set for the device. It contains the
8 information of registers in the same order as described by reg-names.
9 - reg-names: Should contain the reg names
12 - interrupts: Should contain tx and rx interrupt
13 - interrupt-names: Should be "rx" and "tx"
14 - phy-mode: See ethernet.txt file in the same directory.
15 - nvmem-cells: Phandle of nvmem cell containing the MAC address
16 - nvmem-cell-names: Should be "address"
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| D | brcm,systemport.txt | 4 - compatible: should be one of:
5 "brcm,systemport-v1.00"
6 "brcm,systemportlite-v1.00" or
8 - reg: address and length of the register set for the device.
9 - interrupts: interrupts for the device, first cell must be for the rx
11 optional third interrupt cell for Wake-on-LAN can be specified
12 - local-mac-address: Ethernet MAC address (48 bits) of this adapter
13 - phy-mode: Should be a string describing the PHY interface to the
15 - fixed-link: see Documentation/devicetree/bindings/net/fixed-link.txt for
19 - systemport,num-tier2-arb: number of tier 2 arbiters, an integer
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| D | qca,ar71xx.txt | 2 - compatible: Should be "qca,<soc>-eth". Currently support compatibles are:
3 qca,ar7100-eth - Atheros AR7100
4 qca,ar7240-eth - Atheros AR7240
5 qca,ar7241-eth - Atheros AR7241
6 qca,ar7242-eth - Atheros AR7242
7 qca,ar9130-eth - Atheros AR9130
8 qca,ar9330-eth - Atheros AR9330
9 qca,ar9340-eth - Atheros AR9340
10 qca,qca9530-eth - Qualcomm Atheros QCA9530
11 qca,qca9550-eth - Qualcomm Atheros QCA9550
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| D | ethernet-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
16 local-mac-address:
18 - $ref: /schemas/types.yaml#definitions/uint8-array
19 - items:
20 - minItems: 6
25 mac-address:
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| D | brcm,bcmgenet.txt | 4 - compatible: should contain one of "brcm,genet-v1", "brcm,genet-v2",
5 "brcm,genet-v3", "brcm,genet-v4", "brcm,genet-v5".
6 - reg: address and length of the register set for the device
7 - interrupts and/or interrupts-extended: must be two cells, the first cell
10 optional third interrupt cell for Wake-on-LAN can be specified.
11 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
13 - phy-mode: see ethernet.txt file in the same directory
14 - #address-cells: should be 1
15 - #size-cells: should be 1
18 - clocks: When provided, must be two phandles to the functional clocks nodes
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| D | fsl-fec.txt | 4 - compatible : Should be "fsl,<soc>-fec"
5 - reg : Address and length of the register set for the device
6 - interrupts : Should contain fec interrupt
7 - phy-mode : See ethernet.txt file in the same directory
10 - phy-supply : regulator that powers the Ethernet PHY.
11 - phy-handle : phandle to the PHY device connected to this device.
12 - fixed-link : Assume a fixed link. See fixed-link.txt in the same directory.
13 Use instead of phy-handle.
14 - fsl,num-tx-queues : The property is valid for enet-avb IP, which supports
17 - fsl,num-rx-queues : The property is valid for enet-avb IP, which supports
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| D | cpsw.txt | 2 ------------------------------------------------------
5 - compatible : Should be one of the below:-
7 "ti,am335x-cpsw" for AM335x controllers
8 "ti,am4372-cpsw" for AM437x controllers
9 "ti,dra7-cpsw" for DRA7x controllers
10 - reg : physical base address and size of the cpsw
12 - interrupts : property with a value describing the interrupt
14 - cpdma_channels : Specifies number of channels in CPDMA
15 - ale_entries : Specifies No of entries ALE can hold
16 - bd_ram_size : Specifies internal descriptor RAM size
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| D | fsl-tsec-phy.txt | 5 the definition of the PHY node in booting-without-of.txt for an example
9 - reg : Offset and length of the register set for the device, and optionally
14 - compatible : Should define the compatible device type for the
16 - "fsl,gianfar-tbi"
17 - "fsl,gianfar-mdio"
18 - "fsl,etsec2-tbi"
19 - "fsl,etsec2-mdio"
20 - "fsl,ucc-mdio"
21 - "fsl,fman-mdio"
23 - "gianfar"
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| D | ibm,emac.txt | 8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
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| /Documentation/networking/ |
| D | sfp-phylink.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 phylink is a mechanism to support hot-pluggable networking modules
11 directly connected to a MAC without needing to re-initialise the
12 adapter on hot-plug events.
14 phylink supports conventional phylib-based setups, fixed link setups
25 In PHY mode, we use phylib to read the current link settings from
28 negotiation being enabled on the link.
30 2. Fixed mode
32 Fixed mode is the same as PHY mode as far as the MAC driver is
35 3. In-band mode
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| /Documentation/networking/dsa/ |
| D | sja1105.rst | 10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
17 These are SPI-managed automotive switches, with all ports being gigabit
21 set-and-forget use, with minimal dynamic interaction at runtime. They
56 Also the configuration is write-only (software cannot read it back from the
74 interfere with the reception and transmission of real 802.1Q-tagged traffic,
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| D | lan9303.rst | 7 host master network interface (e.g. fixed link).
36 - Support for VLAN filtering is not implemented
37 - The HW does not support VLAN-specific fdb entries
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| /Documentation/block/ |
| D | cmdline-partition.rst | 8 It is typically used for fixed block (eMMC) embedded devices.
15 blkdevparts=<blkdev-def>[;<blkdev-def>]
16 <blkdev-def> := <blkdev-id>:<partdef>[,<partdef>]
17 <partdef> := <size>[@<offset>](part-name)
19 <blkdev-id>
20 block device disk name. Embedded device uses fixed block device.
21 Its disk name is also fixed, such as: mmcblk0, mmcblk1, mmcblk0boot0.
29 "-" is used to denote all remaining space.
37 (part-name)
39 create a link to block device partition with the name "PARTNAME".
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| /Documentation/filesystems/ |
| D | hpfs.txt | 2 1998-2004, Mikulas Patocka
5 homepage: http://artax.karlin.mff.cuni.cz/~mikulas/vyplody/hpfs/index-e.cgi
8 Chris Smith, 1993, original read-only HPFS, some code and hpfs structures file
17 attributes. Mode is inverted umask - for example umask 027 gives owner
24 CR/LF -> LF conversion, if auto, decision is made according to extension
25 - there is a list of text extensions (I thing it's better to not convert
35 corrupted filesystems. check=strict means many superfluous checks -
38 errors=continue,remount-ro,panic (default remount-ro)
43 What to do with extended attributes. 'no' - ignore them and use always
44 values specified in uid/gid/mode options. 'ro' - read extended
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| /Documentation/devicetree/bindings/clock/ |
| D | keystone-pll.txt | 1 Status: Unstable - ABI compatibility may be broken in the future
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
14 - #clock-cells : from common clock binding; shall be set to 0.
15 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
16 - clocks : parent clock phandle
17 - reg - pll control0 and pll multipler registers
18 - reg-names : control, multiplier and post-divider. The multiplier and
19 post-divider registers are applicable only for main pll clock
20 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
25 #clock-cells = <0>;
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| /Documentation/devicetree/bindings/pci/ |
| D | pci.txt | 3 PCI Bus Binding to: IEEE Std 1275-1994
4 http://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
9 http://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
14 - linux,pci-domain:
15 If present this property assigns a fixed PCI domain number to a host bridge,
21 - max-link-speed:
22 If present this property specifies PCI gen for link capability. Host
24 unsupported link speed, for instance, trying to do training for
25 unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2'
27 - reset-gpios:
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