Searched full:gating (Results 1 – 25 of 39) sorted by relevance
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| /Documentation/devicetree/bindings/clock/ |
| D | mvebu-gated-clock.txt | 7 corresponding clock gating control bit in HW to ease manual clock
177 "marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
178 "marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
179 "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
180 "marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
181 "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
182 "marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating
183 "marvell,dove-gating-clock" - for Dove SoC clock gating
184 "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
185 - reg : shall be the register address of the Clock Gating Control register
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| D | zx296718-clk.txt | 10 zx296718 top clock selection, divider and gating
14 zx296718 device level clock selection and gating
17 zx296718 audio clock selection, divider and gating
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| D | zx296702-clk.txt | 10 zx296702 top clock selection, divider and gating
14 zx296702 device level clock selection and gating
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| D | imx8qxp-lpcg.txt | 1 * NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
8 This level of clock gating is provided after the clocks are generated
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| D | ti-keystone-pllctrl.txt | 6 divisions, gating, and synchronization.
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| D | brcm,bcm2835-aux-clock.txt | 7 area controlling clock gating to the peripherals, and providing an IRQ
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| D | imx7ulp-clock.txt | 25 clock gating mode.
39 optional division and clock gating mode for peripherals in their
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| D | lpc1850-creg-clk.txt | 5 32 kHz oscillator driver with power up/down and clock gating. Next
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| D | nvidia,tegra210-car.txt | 7 for muxing and gating Tegra's clocks, and setting their rates.
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| D | altr_socfpga.txt | 22 - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
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| D | nvidia,tegra20-car.txt | 7 for muxing and gating Tegra's clocks, and setting their rates.
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| D | nvidia,tegra30-car.txt | 7 for muxing and gating Tegra's clocks, and setting their rates.
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| D | nvidia,tegra114-car.txt | 7 for muxing and gating Tegra's clocks, and setting their rates.
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| D | renesas,emev2-smu.txt | 27 Clock gating node shown as "Clock stop processing block" in the
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| D | nvidia,tegra124-car.txt | 7 for muxing and gating Tegra's clocks, and setting their rates.
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| /Documentation/devicetree/bindings/power/ |
| D | fsl,imx-gpcv2.txt | 4 The i.MX7S/D General Power Control (GPC) block contains Power Gating
21 described as subnodes of the power gating controller 'pgc' node,
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| D | fsl,imx-gpc.txt | 5 counters and Power Gating Control (PGC).
23 subnodes of the power gating controller 'pgc' node of the GPC and should
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| /Documentation/devicetree/bindings/arm/marvell/ |
| D | kirkwood.txt | 13 where the "powersave" clock is a gating clock used to switch the CPU
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| /Documentation/devicetree/bindings/arm/msm/ |
| D | qcom,idle-state.txt | 13 Standby: Standby does a little more in addition to architectural clock gating.
15 clocks. In addition to gating the clocks, QCOM cpus use this instruction as a
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| /Documentation/arm/sunxi/ |
| D | clocks.rst | 11 A: The 24MHz oscillator allows gating to save power. Indeed, if gated
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| /Documentation/devicetree/bindings/clock/ti/ |
| D | composite.txt | 13 a gating function which can be used to enable and disable the output
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| /Documentation/devicetree/bindings/serial/ |
| D | amlogic,meson-uart.yaml | 19 is active since power-on and does not need any clock gating and is usable
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| /Documentation/devicetree/bindings/clock/ti/davinci/ |
| D | psc.txt | 3 The PSC provides power management, clock gating and reset functionality. It is
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| /Documentation/devicetree/bindings/devfreq/ |
| D | rk3399_dmc.txt | 43 clock gating idle period. Memories are placed
45 clock arg gating started if bus is idle for
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| /Documentation/devicetree/bindings/arm/ |
| D | l2c2x0.yaml | 206 arm,dynamic-clock-gating:
208 L2 dynamic clock gating. Value: <0> (forcibly
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