1* NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings 2 3The Low-Power Clock Gate (LPCG) modules contain a local programming 4model to control the clock gates for the peripherals. An LPCG module 5is used to locally gate the clocks for the associated peripheral. 6 7Note: 8This level of clock gating is provided after the clocks are generated 9by the SCU resources and clock controls. Thus even if the clock is 10enabled by these control bits, it might still not be running based 11on the base resource. 12 13Required properties: 14- compatible: Should be one of: 15 "fsl,imx8qxp-lpcg-adma", 16 "fsl,imx8qxp-lpcg-conn", 17 "fsl,imx8qxp-lpcg-dc", 18 "fsl,imx8qxp-lpcg-dsp", 19 "fsl,imx8qxp-lpcg-gpu", 20 "fsl,imx8qxp-lpcg-hsio", 21 "fsl,imx8qxp-lpcg-img", 22 "fsl,imx8qxp-lpcg-lsio", 23 "fsl,imx8qxp-lpcg-vpu" 24- reg: Address and length of the register set 25- #clock-cells: Should be <1> 26 27The clock consumer should specify the desired clock by having the clock 28ID in its "clocks" phandle cell. 29See the full list of clock IDs from: 30include/dt-bindings/clock/imx8qxp-clock.h 31 32Examples: 33 34#include <dt-bindings/clock/imx8qxp-clock.h> 35 36conn_lpcg: clock-controller@5b200000 { 37 compatible = "fsl,imx8qxp-lpcg-conn"; 38 reg = <0x5b200000 0xb0000>; 39 #clock-cells = <1>; 40}; 41 42usdhc1: mmc@5b010000 { 43 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 44 interrupt-parent = <&gic>; 45 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 46 reg = <0x5b010000 0x10000>; 47 clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK>, 48 <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_PER_CLK>, 49 <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_HCLK>; 50 clock-names = "ipg", "per", "ahb"; 51}; 52