| /Documentation/i2c/busses/ |
| D | index.rst | 4 I2C Bus Drivers
10 i2c-ali1535
11 i2c-ali1563
12 i2c-ali15x3
13 i2c-amd756
14 i2c-amd8111
15 i2c-amd-mp2
16 i2c-diolan-u2c
17 i2c-i801
18 i2c-ismt
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| /Documentation/devicetree/bindings/i2c/ |
| D | nvidia,tegra20-i2c.txt | 1 NVIDIA Tegra20/Tegra30/Tegra114 I2C controller driver.
4 - compatible : For Tegra20, must be one of "nvidia,tegra20-i2c-dvc" or
5 "nvidia,tegra20-i2c". For Tegra30, must be "nvidia,tegra30-i2c".
6 For Tegra114, must be "nvidia,tegra114-i2c". Otherwise, must be
7 "nvidia,<chip>-i2c", plus at least one of the above, where <chip> is
10 nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C
11 controller. This only support master mode of I2C communication. Register
12 interface/offset and interrupts handling are different than generic I2C
13 controller. Driver of DVC I2C controller is only compatible with
14 "nvidia,tegra20-i2c-dvc".
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| D | renesas,i2c.txt | 1 I2C for R-Car platforms
5 "renesas,i2c-r8a7743" if the device is a part of a R8A7743 SoC.
6 "renesas,i2c-r8a7744" if the device is a part of a R8A7744 SoC.
7 "renesas,i2c-r8a7745" if the device is a part of a R8A7745 SoC.
8 "renesas,i2c-r8a77470" if the device is a part of a R8A77470 SoC.
9 "renesas,i2c-r8a774a1" if the device is a part of a R8A774A1 SoC.
10 "renesas,i2c-r8a774c0" if the device is a part of a R8A774C0 SoC.
11 "renesas,i2c-r8a7778" if the device is a part of a R8A7778 SoC.
12 "renesas,i2c-r8a7779" if the device is a part of a R8A7779 SoC.
13 "renesas,i2c-r8a7790" if the device is a part of a R8A7790 SoC.
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| D | i2c-imx.txt | 1 * Freescale Inter IC (I2C) and High Speed Inter IC (HS-I2C) for i.MX
5 - "fsl,imx1-i2c" for I2C compatible with the one integrated on i.MX1 SoC
6 - "fsl,imx21-i2c" for I2C compatible with the one integrated on i.MX21 SoC
7 - "fsl,vf610-i2c" for I2C compatible with the one integrated on Vybrid vf610 SoC
8 - reg : Should contain I2C/HS-I2C registers location and length
9 - interrupts : Should contain I2C/HS-I2C interrupt
10 - clocks : Should contain the I2C/HS-I2C clock specifier
13 - clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz.
19 - pinctrl: add extra pinctrl to configure i2c pins to gpio function for i2c
24 i2c@83fc4000 { /* I2C2 on i.MX51 */
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| D | marvell,mv64xxx-i2c.yaml | 4 $id: http://devicetree.org/schemas/i2c/marvell,mv64xxx-i2c.yaml#
7 title: Marvell MV64XXX I2C Controller Device Tree Bindings
15 - const: allwinner,sun4i-a10-i2c
17 - const: allwinner,sun7i-a20-i2c
18 - const: allwinner,sun4i-a10-i2c
19 - const: allwinner,sun6i-a31-i2c
21 - const: allwinner,sun8i-a23-i2c
22 - const: allwinner,sun6i-a31-i2c
24 - const: allwinner,sun8i-a83t-i2c
25 - const: allwinner,sun6i-a31-i2c
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| D | i2c-mt65xx.txt | 1 * MediaTek's I2C controller
3 The MediaTek's I2C controller is used to interface with I2C devices.
7 "mediatek,mt2701-i2c", "mediatek,mt6577-i2c": for MediaTek MT2701
8 "mediatek,mt2712-i2c": for MediaTek MT2712
9 "mediatek,mt6577-i2c": for MediaTek MT6577
10 "mediatek,mt6589-i2c": for MediaTek MT6589
11 "mediatek,mt7622-i2c": for MediaTek MT7622
12 "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623
13 "mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629
14 "mediatek,mt8173-i2c": for MediaTek MT8173
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| D | i2c-rk3x.txt | 1 * Rockchip RK3xxx I2C controller
3 This driver interfaces with the native I2C controller present in Rockchip
10 - "rockchip,rv1108-i2c": for rv1108
11 - "rockchip,rk3066-i2c": for rk3066
12 - "rockchip,rk3188-i2c": for rk3188
13 - "rockchip,rk3228-i2c": for rk3228
14 - "rockchip,rk3288-i2c": for rk3288
15 - "rockchip,rk3328-i2c", "rockchip,rk3399-i2c": for rk3328
16 - "rockchip,rk3399-i2c": for rk3399
23 - "i2c": This is used to derive the functional clock.
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| D | i2c-s3c2410.txt | 1 * Samsung's I2C controller
3 The Samsung's I2C controller is used to interface with I2C devices.
7 (a) "samsung, s3c2410-i2c", for i2c compatible with s3c2410 i2c.
8 (b) "samsung, s3c2440-i2c", for i2c compatible with s3c2440 i2c.
9 (c) "samsung, s3c2440-hdmiphy-i2c", for s3c2440-like i2c used
11 (d) "samsung, exynos5-sata-phy-i2c", for s3c2440-like i2c used as
16 - samsung,i2c-sda-delay: Delay (in ns) applied to data line (SDA) edges.
18 Required for all cases except "samsung,s3c2440-hdmiphy-i2c":
22 cases except for "samsung,s3c2440-hdmiphy-i2c" whose input/output
29 - samsung,i2c-slave-addr: Slave address in multi-master environment. If not
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| D | i2c-mux-gpmux.txt | 1 General Purpose I2C Bus Mux
3 This binding describes an I2C bus multiplexer that uses a mux controller
4 from the mux subsystem to route the I2C signals.
12 | | I2C |-|--| Mux |
21 - compatible: i2c-mux
22 - i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
26 * Standard I2C mux properties. See i2c-mux.txt in this directory.
27 * I2C child bus nodes. See i2c-mux.txt in this directory. The sub-bus number
31 - mux-locked: If present, explicitly allow unrelated I2C transactions on the
32 parent I2C adapter at these times:
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| D | i2c-at91.txt | 1 I2C for Atmel platforms
4 - compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c",
5 "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c",
6 "atmel,at91sam9x5-i2c", "atmel,sama5d4-i2c" or "atmel,sama5d2-i2c"
15 - clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000
19 capable I2C controllers.
20 - i2c-sda-hold-time-ns: TWD hold time, only available for "atmel,sama5d4-i2c"
21 and "atmel,sama5d2-i2c".
22 - Child nodes conforming to i2c bus binding
26 i2c0: i2c@fff84000 {
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| D | nvidia,tegra186-bpmp-i2c.txt | 1 NVIDIA Tegra186 BPMP I2C controller
4 devices, such as the I2C controller for the power management I2C bus. Software
6 transactions on that I2C bus. This binding describes an I2C bus that is
9 The BPMP I2C node must be located directly inside the main BPMP node. See
12 This node represents an I2C controller. See ../i2c/i2c.txt for details of the
13 core I2C binding.
19 - "nvidia,tegra186-bpmp-i2c".
20 - #address-cells: Address cells for I2C device address.
28 Indicates the I2C bus number this DT node represent, as defined by the
36 i2c {
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| D | i2c-sprd.txt | 1 I2C for Spreadtrum platforms
4 - compatible: Should be "sprd,sc9860-i2c".
7 - interrupts: Should contain I2C interrupt.
9 "i2c" for I2C clock,
10 "source" for I2C source (parent) clock,
11 "enable" for I2C module enable clock.
13 - clock-frequency: Constains desired I2C bus clock frequency in Hz.
14 - #address-cells: Should be 1 to describe address cells for I2C device address.
15 - #size-cells: Should be 0 means no size cell for I2C device address.
18 - Child nodes conforming to I2C bus binding
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| D | i2c-mux.txt | 1 Common i2c bus multiplexer/switch properties.
3 An i2c bus multiplexer/switch will have several child busses that are
4 numbered uniquely in a device dependent manner. The nodes for an i2c bus
9 This property is required if the i2c-mux child node does not exist.
12 This property is required if the i2c-mux child node does not exist.
14 - i2c-mux
15 For i2c multiplexers/switches that have child nodes that are a mixture
16 of both i2c child busses and other child nodes, the 'i2c-mux' subnode
17 can be used for populating the i2c child busses. If an 'i2c-mux'
18 subnode is present, only subnodes of this will be considered as i2c
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| D | i2c-omap.txt | 1 I2C for OMAP platforms
5 "ti,omap2420-i2c" for OMAP2420 SoCs
6 "ti,omap2430-i2c" for OMAP2430 SoCs
7 "ti,omap3-i2c" for OMAP3 SoCs
8 "ti,omap4-i2c" for OMAP4+ SoCs
9 "ti,am654-i2c", "ti,omap4-i2c" for AM654 SoCs
10 "ti,j721e-i2c", "ti,omap4-i2c" for J721E SoCs
11 - ti,hwmods : Must be "i2c<n>", n being the instance number (1-based)
16 - clock-frequency : Desired I2C bus clock frequency in Hz. Otherwise
20 - Child nodes conforming to i2c bus binding
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| D | i2c-demux-pinctrl.txt | 1 Pinctrl-based I2C Bus DeMux
3 This binding describes an I2C bus demultiplexer that uses pin multiplexing to
4 route the I2C signals, and represents the pin multiplexing configuration using
5 the pinctrl device tree bindings. This may be used to select one I2C IP core at
6 runtime which may have a better feature set for a given task than another I2C
14 | |I2C IP Core1|--\ | +-----+ +-----+
18 | |I2C IP Core2|--/ |
24 - compatible: "i2c-demux-pinctrl"
25 - i2c-parent: List of phandles of I2C masters available for selection. The first
27 - i2c-bus-name: The name of this bus. Also needed as pinctrl-name for the I2C
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| D | i2c.txt | 1 Generic device tree bindings for I2C busses
4 This document describes generic bindings which can be used to describe I2C
12 - compatible - name of I2C bus controller following generic names
18 The cells properties above define that an address of children of an I2C bus
35 - i2c-bus
36 For I2C adapters that have child nodes that are a mixture of both I2C
37 devices and non-I2C devices, the 'i2c-bus' subnode can be used for
38 populating I2C devices. If the 'i2c-bus' subnode is present, only
39 subnodes of this will be considered as I2C slaves. The properties,
43 - i2c-scl-falling-time-ns
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| D | i2c-designware.txt | 1 * Synopsys DesignWare I2C
5 - compatible : should be "snps,designware-i2c"
6 or "mscc,ocelot-i2c" with "snps,designware-i2c" for fallback
16 - clock-frequency : desired I2C bus clock frequency in Hz.
21 "ic_clk", for the core clock used to generate the external I2C clock.
24 - reg : for "mscc,ocelot-i2c", a second register set to configure the SDA hold
27 - i2c-sda-hold-time-ns : should contain the SDA hold time in nanoseconds.
29 on Microsemi SoCs ("mscc,ocelot-i2c" compatible).
31 - i2c-scl-falling-time-ns : should contain the SCL falling time in nanoseconds.
34 - i2c-sda-falling-time-ns : should contain the SDA falling time in nanoseconds.
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| D | i2c-stm32.txt | 1 * I2C controller embedded in STMicroelectronics STM32 I2C platform
5 - "st,stm32f4-i2c"
6 - "st,stm32f7-i2c"
8 - interrupts: Must contain the interrupt id for I2C event and then the
9 interrupt id for I2C error.
11 - clocks: Must contain the input clock of the I2C instance.
13 operation for I2C transfer
18 - clock-frequency: Desired I2C bus clock frequency in Hz. If not specified,
26 - i2c-scl-rising-time-ns: I2C SCL Rising time for the board (default: 25)
28 - i2c-scl-falling-time-ns: I2C SCL Falling time for the board (default: 10)
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| /Documentation/devicetree/bindings/ |
| D | unittest.txt | 15 2) OF unittest i2c adapter platform device
20 - compatible: must be unittest-i2c-bus
22 Children nodes contain unittest i2c devices.
25 unittest-i2c-bus {
26 compatible = "unittest-i2c-bus";
29 3) OF unittest i2c device
31 ** I2C unittest device
34 - compatible: must be unittest-i2c-dev
39 unittest-i2c-dev {
40 compatible = "unittest-i2c-dev";
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| D | trivial-devices.yaml | 7 title: Trivial I2C and SPI devices that have simple device tree bindings
13 This is a list of trivial I2C and SPI devices that have simple device tree
29 … # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
51 # i2c serial eeprom (24cxx)
53 # i2c trusted platform module (TPM)
55 # i2c h/w symmetric crypto module
57 # i2c h/w elliptic curve crypto module
73 # Devantech SRF02 ultrasonic ranger in I2C mode
101 # Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz)
103 # Infineon SLB9645 I2C TPM (new protocol, max 400khz)
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/ |
| D | i2c.txt | 1 * I2C
3 The I2C controller is expressed as a bus under the CPM node.
6 - compatible : "fsl,cpm1-i2c", "fsl,cpm2-i2c"
7 - reg : On CPM2 devices, the second resource doesn't specify the I2C
10 - #address-cells : Should be one. The cell is the i2c device address with
13 - clock-frequency : Can be used to set the i2c clock frequency. If
16 i2c drivers to find the bus to probe:
17 - linux,i2c-index : Can be used to hard code an i2c bus number. By default,
18 the bus number is dynamically assigned by the i2c core.
19 - linux,i2c-class : Can be used to override the i2c class. The class is used
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| /Documentation/driver-api/ |
| D | i2c.rst | 4 I\ :sup:`2`\ C (or without fancy typography, "I2C") is an acronym for
8 the same bus. I2C only needs two signals (SCL for clock, SDA for data),
10 I2C devices use seven bit addresses, and bus speeds of up to 400 kHz;
12 I2C is a multi-master bus; open drain signaling is used to arbitrate
16 The Linux I2C programming interfaces support the master side of bus
18 structured around two kinds of driver, and two kinds of device. An I2C
22 I2C bus segment it manages. On each I2C bus segment will be I2C devices
26 are functions to perform various I2C protocol operations; at this writing
30 systems are also I2C conformant. The electrical constraints are tighter
32 Controllers that support I2C can also support most SMBus operations, but
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| /Documentation/i2c/ |
| D | instantiating-devices.rst | 2 How to instantiate I2C devices
5 Unlike PCI or USB devices, I2C devices are not enumerated at the hardware
7 I2C bus segment, and what address these devices are using. For this
8 reason, the kernel code must instantiate I2C devices explicitly. There are
12 Method 1a: Declare the I2C devices by bus number
15 This method is appropriate when the I2C bus is a system bus as is the case
16 for many embedded systems. On such systems, each I2C bus has a number
17 which is known in advance. It is thus possible to pre-declare the I2C
46 The above code declares 3 devices on I2C bus 1, including their respective
47 addresses and custom data needed by their drivers. When the I2C bus in
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| D | dev-interface.rst | 2 I2C Device Interface
5 Usually, i2c devices are controlled by a kernel driver. But it is also
7 the /dev interface. You need to load module i2c-dev for this.
9 Each registered i2c adapter gets a number, counting from 0. You can
10 examine /sys/class/i2c-dev/ to see what number corresponds to which adapter.
12 i2c adapters present on your system at a given time. i2cdetect is part of
13 the i2c-tools package.
15 I2C device files are character device files with major device number 89
17 explained above. They should be called "i2c-%d" (i2c-0, i2c-1, ...,
18 i2c-10, ...). All 256 minor device numbers are reserved for i2c.
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| D | summary.rst | 2 I2C and SMBus
5 I2C (pronounce: I squared C) is a protocol developed by Philips. It is a
9 I2C is widely used with embedded systems. Some systems use variants that
10 don't meet branding requirements, and so are not advertised as being I2C.
12 SMBus (System Management Bus) is based on the I2C protocol, and is mostly
13 a subset of I2C protocols and signaling. Many I2C devices will work on an
15 achieve I2C branding. Modern PC mainboards rely on SMBus. The most common
16 devices connected through SMBus are RAM modules configured using I2C EEPROMs,
19 Because the SMBus is mostly a subset of the generalized I2C bus, we can
20 use its protocols on many I2C systems. However, there are systems that don't
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