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/Documentation/
Dthis_cpu_ops.txt8 this_cpu operations are a way of optimizing access to per cpu
9 variables associated with the *currently* executing processor. This is
11 the cpu permanently stored the beginning of the per cpu area for a
12 specific processor).
14 this_cpu operations add a per cpu variable offset to the processor
15 specific per cpu base and encode that operation in the instruction
16 operating on the per cpu variable.
21 processor is not changed between the calculation of the address and
24 Read-modify-write operations are of particular interest. Frequently
32 synchronization is not necessary since we are dealing with per cpu
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/Documentation/devicetree/bindings/remoteproc/
Dti,keystone-rproc.txt5 sub-systems that are used to offload some of the processor-intensive tasks or
8 These processor sub-systems usually contain additional sub-modules like L1
10 a dedicated local power/sleep controller etc. The DSP processor core in
11 Keystone 2 SoCs is usually a TMS320C66x CorePac processor.
15 Each DSP Core sub-system is represented as a single DT node, and should also
17 or optional properties that enable the OS running on the host processor (ARM
18 CorePac) to perform the device management of the remote processor and to
19 communicate with the remote processor.
22 --------------------
25 - compatible: Should be one of the following,
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Dti,davinci-rproc.txt4 Binding status: Unstable - Subject to changes for DT representation of clocks
7 The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that
8 is used to offload some of the processor-intensive tasks or algorithms, for
11 The processor cores in the sub-system usually contain additional sub-modules
13 controller, a dedicated local power/sleep controller etc. The DSP processor
18 Each DSP Core sub-system is represented as a single DT node.
21 --------------------
24 - compatible: Should be one of the following,
25 "ti,da850-dsp" for DSPs on OMAP-L138 SoCs
27 - reg: Should contain an entry for each value in 'reg-names'.
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/Documentation/admin-guide/pm/
Dintel_pstate.rst1 .. SPDX-License-Identifier: GPL-2.0
24 For the processors supported by ``intel_pstate``, the P-state concept is broader
27 information about that). For this reason, the representation of P-states used
32 ``intel_pstate`` maps its internal representation of P-states to frequencies too
38 Since the hardware P-state selection interface used by ``intel_pstate`` is
43 time the corresponding CPU is taken offline and need to be re-initialized when
47 only way to pass early-configuration-time parameters to it is via the kernel
58 or without hardware-managed P-states support and in the passive mode. Which of
60 on the capabilities of the processor.
63 -----------
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/Documentation/devicetree/bindings/timer/
Dsamsung,exynos4210-mct.txt4 global timer and CPU local timers. The global timer is a 64-bit free running
5 up-counter and can generate 4 interrupts when the counter reaches one of the
6 four preset counter values. The CPU local timers are 32-bit free running
7 down-counters and generate an interrupt when the counter expires. There is
12 - compatible: should be "samsung,exynos4210-mct".
13 (a) "samsung,exynos4210-mct", for mct compatible with Exynos4210 mct.
14 (b) "samsung,exynos4412-mct", for mct compatible with Exynos4412 mct.
16 - reg: base address of the mct controller and length of the address space
19 - interrupts: the list of interrupts generated by the controller. The following
34 For MCT block that uses a per-processor interrupt for local timers, such
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Darm,twd.txt3 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
4 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
7 The TWD is usually attached to a GIC to deliver its two per-processor
12 - compatible : Should be one of:
13 "arm,cortex-a9-twd-timer"
14 "arm,cortex-a5-twd-timer"
15 "arm,arm11mp-twd-timer"
17 - interrupts : One interrupt to each core
19 - reg : Specify the base address and the size of the TWD timer
24 - always-on : a boolean property. If present, the timer is powered through
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Darm,arch_timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
15 physical and optional virtual timer per frame.
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
24 - items:
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/Documentation/devicetree/bindings/watchdog/
Dzii,rave-sp-wdt.txt1 Zodiac Inflight Innovations RAVE Supervisory Processor Watchdog Bindings
4 watchdog functionality of RAVE Supervisory Processor. It is expected
7 Documentation/devicetree/bindings/mfd/zii,rave-sp.txt)
11 - compatible: Depending on wire protocol implemented by RAVE SP
13 - "zii,rave-sp-watchdog"
14 - "zii,rave-sp-watchdog-legacy"
18 - wdt-timeout: Two byte nvmem cell specified as per
23 rave-sp {
24 compatible = "zii,rave-sp-rdu1";
25 current-speed = <38400>;
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/Documentation/admin-guide/acpi/
Dcppc_sysfs.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Collaborative Processor Performance Control (CPPC)
11 performance of a logical processor on a contigious and abstract performance
13 to request performance levels and to measure per-cpu delivered performance.
25 $ ls -lR /sys/devices/system/cpu/cpu0/acpi_cppc/
28 -r--r--r-- 1 root root 65536 Mar 5 19:38 feedback_ctrs
29 -r--r--r-- 1 root root 65536 Mar 5 19:38 highest_perf
30 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_freq
31 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_nonlinear_perf
32 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_perf
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/Documentation/devicetree/bindings/display/
Darm,malidp.txt1 ARM Mali-DP
9 - compatible: should be one of
10 "arm,mali-dp500"
11 "arm,mali-dp550"
12 "arm,mali-dp650"
14 - reg: Physical base address and size of the block of registers used by
15 the processor.
16 - interrupts: Interrupt list, as defined in ../interrupt-controller/interrupts.txt,
18 - interrupt-names: name of the engine inside the processor that will
20 - clocks: A list of phandle + clock-specifier pairs, one for each entry
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/Documentation/virt/kvm/devices/
Dxics.txt7 Attributes: One per interrupt source, indexed by the source number.
11 sources, each identified by a 20-bit source number, and a set of
22 least-significant end of the word:
29 * Pending IPI (inter-processor interrupt) priority, 8 bits
35 * Current processor priority, 8 bits
43 bitfields, starting from the least-significant end of the word:
55 This bit is 1 for a level-sensitive interrupt source, or 0 for
56 edge-sensitive (or MSI).
60 regardless of its priority), for example by the ibm,int-off RTAS
66 Only one XICS instance may be created per VM.
/Documentation/userspace-api/accelerators/
Docxl.rst2 OpenCAPI (Open Coherent Accelerator Processor Interface)
6 at being low-latency and high-bandwidth. The specification is
14 OpenCAPI is known in linux as 'ocxl', as the open, processor-agnostic
20 High-level view
24 be implemented on top of a physical link. Any processor or device
29 +-----------+ +-------------+
32 | Processor | | Function |
33 | | +--------+ | Unit | +--------+
34 | |--| Memory | | (AFU) |--| Memory |
35 | | +--------+ | | +--------+
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/Documentation/admin-guide/perf/
Darm-ccn.rst5 CCN-504 is a ring-bus interconnect consisting of 11 crosspoints
11 -----------------
29 Crosspoint watchpoint-based events (special "event" value 0xfe)
43 a single CPU ID, of the processor which will be used to handle all
45 request the events on this processor (if not, the perf_event->cpu value
46 will be overwritten anyway). In case of this processor being offlined,
57 / # perf stat -a -e ccn/cycles/,ccn/xp_valid_flit,xp=1,port=0,vc=1,dir=1/ \
61 not work. Per-task (without "-a") perf sessions are not supported.
/Documentation/devicetree/bindings/interrupt-controller/
Dopenrisc,ompic.txt1 Open Multi-Processor Interrupt Controller
5 - compatible : This should be "openrisc,ompic"
6 - reg : Specifies base physical address and size of the register space. The
8 to handle, this should be set to 8 bytes per cpu core.
9 - interrupt-controller : Identifies the node as an interrupt controller.
10 - #interrupt-cells : This should be set to 0 as this will not be an irq
12 - interrupts : Specifies the interrupt line to which the ompic is wired.
16 ompic: interrupt-controller@98000000 {
19 interrupt-controller;
20 #interrupt-cells = <0>;
Darm,nvic.txt4 Cortex-M based processor cores. The NVIC implemented on different SoCs
5 vary in the number of interrupts and priority bits per interrupt.
9 - compatible : should be one of:
10 "arm,v6m-nvic"
11 "arm,v7m-nvic"
12 "arm,v8m-nvic"
13 - interrupt-controller : Identifies the node as an interrupt controller
14 - #interrupt-cells : Specifies the number of cells needed to encode an
21 - reg : Specifies base physical address(s) and size of the NVIC registers.
24 - arm,num-irq-priority-bits: The number of priority bits implemented by the
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Dmips-gic.txt4 It also supports local (per-processor) interrupts and software-generated
5 interrupts which can be used as IPIs. The GIC also includes a free-running
6 global timer, per-CPU count/compare timers, and a watchdog.
9 - compatible : Should be "mti,gic".
10 - interrupt-controller : Identifies the node as an interrupt controller
11 - #interrupt-cells : Specifies the number of cells needed to encode an
13 - The first cell is the type of interrupt, local or shared.
14 See <include/dt-bindings/interrupt-controller/mips-gic.h>.
15 - The second cell is the GIC interrupt number.
16 - The third cell encodes the interrupt flags.
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/Documentation/hwmon/
Dcoretemp.rst11 - 0xe (Pentium M DC), 0xf (Core 2 DC 65nm),
12 - 0x16 (Core 2 SC 65nm), 0x17 (Penryn 45nm),
13 - 0x1a (Nehalem), 0x1c (Atom), 0x1e (Lynnfield),
14 - 0x26 (Tunnel Creek Atom), 0x27 (Medfield Atom),
15 - 0x36 (Cedar Trail Atom)
19 Intel 64 and IA-32 Architectures Software Developer's Manual
27 -----------
30 inside Intel CPUs. This driver can read both the per-core and per-package
31 temperature using the appropriate sensors. The per-package sensor is new;
40 Temperature known as TjMax is the maximum junction temperature of processor,
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Dasb100.rst6 * Asus ASB100 and ASB100-A "Bach"
17 -----------
19 This driver implements support for the Asus ASB100 and ASB100-A "Bach".
30 these, the ASB100-A also implements a single PWM controller for fans 2 and
37 Fan speeds are reported in RPM (rotations per minute). An alarm is
43 processor should work with. This is hardcoded by the mainboard and/or
44 processor itself. It is a value in volts.
48 - 0x0001 => in0 (?)
49 - 0x0002 => in1 (?)
50 - 0x0004 => in2
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Dasc7621.rst20 Andigilog has both the PECI and pre-PECI versions of the Heceta-6, as
21 Intel calls them. Heceta-6e has high frequency PWM and Heceta-6p has
23 Heceta-6e part and aSC7621 is the Heceta-6p part. They are both in
28 have used registers below 20h for vendor-specific functions in addition
29 to those in the Intel-specified vendor range.
32 The fan speed control uses this finer value to produce a "step-less" fan
33 PWM output. These two bytes are "read-locked" to guarantee that once a
34 high or low byte is read, the other byte is locked-in until after the
37 sheet says 10-bits of resolution, although you may find the lower bits
47 We offer GPIO features on the former VID pins. These are open-drain
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Dlm78.rst6 * National Semiconductor LM78 / LM78-J
10 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports)
20 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports)
28 - Frodo Looijaard <frodol@dds.nl>
29 - Jean Delvare <jdelvare@suse.de>
32 -----------
34 This driver implements support for the National Semiconductor LM78, LM78-J
38 the LM78 and LM78-J are exactly identical. The LM79 has one more VID line,
51 between -55 and +125 degrees, with a resolution of 1 degree.
53 Fan rotation speeds are reported in RPM (rotations per minute). An alarm is
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/Documentation/devicetree/bindings/mailbox/
Domap-mailbox.txt6 various processor subsystems and is connected on an interconnect bus. The
12 within a processor subsystem, and there can be more than one line going to a
13 specific processor's interrupt controller. The interrupt line connections are
17 and tx interrupt source per h/w fifo. Communication between different processors
25 routed to different processor sub-systems on DRA7xx as they are routed through
29 all these clusters are multiplexed and routed to different processor subsystems
35 a SoC. The sub-mailboxes are represented as child nodes of this parent node.
38 --------------------
39 - compatible: Should be one of the following,
40 "ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs
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/Documentation/scheduler/
Dsched-stats.rst11 12 which was in the kernel from 2.6.13-2.6.19 (version 13 never saw a kernel
12 release). Some counters make more sense to be per-runqueue; other to be
13 per-domain. Note that domains (and their associated information) will only
33 Note that any such script will necessarily be version-specific, as the main
38 --------------
50 4) # of times schedule() left the processor idle
59 7) sum of all time spent running by tasks on this processor (in jiffies)
60 8) sum of all time spent waiting to run by tasks on this processor (in
66 -----------------
67 One of these is produced per domain for each cpu described. (Note that if
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/Documentation/devicetree/bindings/arm/msm/
Dqcom,kpss-acc.txt1 Krait Processor Sub-system (KPSS) Application Clock Controller (ACC)
4 There is one ACC register region per CPU within the KPSS remapped region as
10 - compatible:
14 "qcom,kpss-acc-v1"
15 "qcom,kpss-acc-v2"
17 - reg:
19 Value type: <prop-encoded-array>
24 - clocks:
26 Value type: <prop-encoded-array>
29 - clock-names:
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/Documentation/cpu-freq/
Dcpu-drivers.txt8 - information for developers -
23 ---------
26 1.2 Per-CPU Initialization
39 So, you just got a brand-new CPU / chipset with datasheets and want to
45 ------------------
54 .name - The name of this driver.
56 .init - A pointer to the per-policy initialization function.
58 .verify - A pointer to a "verification" function.
60 .setpolicy _or_ .fast_switch _or_ .target _or_ .target_index - See
65 .flags - Hints for the cpufreq core.
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/Documentation/powerpc/
Ddscr.rst6 stream in the processor. Please refer to the ISA documents or related manual
21 dscr_default /* per-CPU DSCR default value */
29 Scheduler will write the per-CPU DSCR default which is stored in the
35 the per-CPU default PACA based DSCR value.
42 - Global DSCR default: /sys/devices/system/cpu/dscr_default
43 - CPU specific DSCR default: /sys/devices/system/cpu/cpuN/dscr
60 (1) Problem state SPR: 0x03 (Un-privileged, POWER8 only)

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