| /Documentation/driver-api/phy/ |
| D | phy.rst | 2 PHY subsystem
7 This document explains the Generic PHY Framework along with the APIs provided,
13 *PHY* is the abbreviation for physical layer. It is used to connect a device
14 to the physical medium e.g., the USB controller has a PHY to provide functions
17 controllers have PHY functionality embedded into it and others use an external
18 PHY. Other peripherals that use PHY include Wireless LAN, Ethernet,
21 The intention of creating this framework is to bring the PHY drivers spread
22 all over the Linux kernel to drivers/phy to increase code re-use and for
25 This framework will be of use only to devices that use external PHY (PHY
28 Registering/Unregistering the PHY provider
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| /Documentation/devicetree/bindings/phy/ |
| D | brcm,stingray-usb-phy.txt | 1 Broadcom Stingray USB PHY
5 - "brcm,sr-usb-combo-phy" is combo PHY has two PHYs, one SS and one HS.
6 - "brcm,sr-usb-hs-phy" is a single HS PHY.
7 - reg: offset and length of the PHY blocks registers
8 - #phy-cells:
9 - Must be 1 for brcm,sr-usb-combo-phy as it expects one argument to indicate
10 the PHY number of two PHYs. 0 for HS PHY and 1 for SS PHY.
11 - Must be 0 for brcm,sr-usb-hs-phy.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties
16 usbphy0: usb-phy@0 {
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| D | samsung-phy.txt | 6 - "samsung,s5pv210-mipi-video-phy"
7 - "samsung,exynos5420-mipi-video-phy"
8 - "samsung,exynos5433-mipi-video-phy"
9 - #phy-cells : from the generic phy bindings, must be 1;
14 In case of exynos5433 compatible PHY:
20 For "samsung,s5pv210-mipi-video-phy" compatible PHYs the second cell in
21 the PHY specifier identifies the PHY and its meaning is as follows:
26 "samsung,exynos5420-mipi-video-phy" and "samsung,exynos5433-mipi-video-phy"
27 supports additional fifth PHY:
30 Samsung EXYNOS SoC series Display Port PHY
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| D | qcom-qmp-phy.txt | 1 Qualcomm QMP PHY controller
4 QMP phy controller supports physical layer functionality for a number of
9 "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
10 "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
11 "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
12 "qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998,
13 "qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998,
14 "qcom,msm8998-qmp-pcie-phy" for PCIe QMP phy on msm8998,
15 "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
16 "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
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| D | brcm-sata-phy.txt | 1 * Broadcom SATA3 PHY
5 "brcm,bcm7425-sata-phy"
6 "brcm,bcm7445-sata-phy"
7 "brcm,iproc-ns2-sata-phy"
8 "brcm,iproc-nsp-sata-phy"
9 "brcm,phy-sata3"
10 "brcm,iproc-sr-sata-phy"
11 "brcm,bcm63138-sata-phy"
14 - reg: register ranges for the PHY PCB interface
15 - reg-names: should be "phy" and "phy-ctrl"
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| D | phy-bindings.txt | 2 information about PHY subsystem refer to Documentation/driver-api/phy/phy.rst
4 PHY device node
8 #phy-cells: Number of cells in a PHY specifier; The meaning of all those
9 cells is defined by the binding for the phy node. The PHY
11 PHY.
14 phy-supply: Phandle to a regulator that provides power to the PHY. This
15 regulator will be managed during the PHY power on/off sequence.
19 phys: phy {
24 #phy-cells = <1>;
29 That node describes an IP block (PHY provider) that implements 2 different PHYs.
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| D | phy-hisi-inno-usb2.txt | 1 Device tree bindings for HiSilicon INNO USB2 PHY
5 "hisilicon,inno-usb2-phy",
6 "hisilicon,hi3798cv200-usb2-phy".
7 - reg: Should be the address space for PHY configuration register in peripheral
9 - clocks: The phandle and clock specifier pair for INNO USB2 PHY device
11 - resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
16 The INNO USB2 PHY device should be a child node of peripheral controller that
17 contains the PHY configuration register, and each device suppports up to 2 PHY
18 ports which are represented as child nodes of INNO USB2 PHY device.
20 Required properties for PHY port node:
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| D | phy-stm32-usbphyc.txt | 1 STMicroelectronics STM32 USB HS PHY controller
3 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
4 switch. It controls PHY configuration and status, and the UTMI+ switch that
5 selects either OTG or HOST controller for the second PHY port. It also sets
11 |_ PHY port#1 _________________ HOST controller
14 |_ PHY port#2 ----| |________________
19 Phy provider node
24 - reg: address and length of the usb phy control register set
25 - clocks: phandle + clock specifier for the PLL phy clock
30 - assigned-clocks: phandle + clock specifier for the PLL phy clock
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| D | qcom-qusb2-phy.txt | 1 Qualcomm QUSB2 phy controller
8 "qcom,msm8996-qusb2-phy" for 14nm PHY on msm8996,
9 "qcom,msm8998-qusb2-phy" for 10nm PHY on msm8998,
10 "qcom,sdm845-qusb2-phy" for 10nm PHY on sdm845.
12 - reg: offset and length of the PHY register set.
13 - #phy-cells: must be 0.
17 - clock-names: must be "cfg_ahb" for phy config clock,
19 "iface" for phy interface clock (Optional).
21 - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
22 - vdda-phy-dpdm-supply: Phandle to 3.1V regulator supply to Dp/Dm port signals.
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| D | ti-phy.txt | 1 TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
3 OMAP CONTROL PHY
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
11 e.g. USB3 PHY and SATA PHY on OMAP5.
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
14 e.g. PCIE PHY in DRA7x
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
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| D | uniphier-usb2-phy.txt | 1 Socionext UniPhier USB2 PHY
3 This describes the devicetree bindings for PHY interface built into
7 controller doesn't include its own High-Speed PHY. This needs to specify
8 USB2 PHY instead of USB3 HS-PHY.
12 "socionext,uniphier-pro4-usb2-phy" - for Pro4 SoC
13 "socionext,uniphier-ld11-usb2-phy" - for LD11 SoC
16 Each PHY should be represented as a sub-node.
19 - #phy-cells: Should be 0.
20 - reg: The number of the PHY.
25 Refer to phy/phy-bindings.txt for the generic PHY binding properties.
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| D | brcm,cygnus-pcie-phy.txt | 1 Broadcom Cygnus PCIe PHY
4 - compatible: must be "brcm,cygnus-pcie-phy"
5 - reg: base address and length of the PCIe PHY block
9 Each PCIe PHY should be represented by a child node
12 - reg: the PHY ID
15 - #phy-cells: must be 0
18 pcie_phy: phy@301d0a0 {
19 compatible = "brcm,cygnus-pcie-phy";
22 pcie0_phy: phy@0 {
24 #phy-cells = <0>;
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| D | uniphier-pcie-phy.txt | 1 Socionext UniPhier PCIe PHY bindings
3 This describes the devicetree bindings for PHY interface built into
8 "socionext,uniphier-ld20-pcie-phy" - for LD20 PHY
9 "socionext,uniphier-pxs3-pcie-phy" - for PXs3 PHY
11 - #phy-cells: Must be zero.
13 this phy.
15 this phy.
19 for phy.
21 Refer to phy/phy-bindings.txt for the generic PHY binding properties.
24 pcie_phy: phy@66038000 {
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| D | lantiq,vrx200-pcie-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
7 title: Lantiq VRX200 and ARX300 PCIe PHY Device Tree Bindings
13 "#phy-cells":
15 description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
19 - lantiq,vrx200-pcie-phy
20 - lantiq,arx300-pcie-phy
27 - description: PHY module clock
32 - const: phy
37 - description: exclusive PHY reset line
38 - description: shared reset line between the PCIe PHY and PCIe controller
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| D | rockchip-usb-phy.txt | 1 ROCKCHIP USB2 PHY
5 "rockchip,rk3066a-usb-phy"
6 "rockchip,rk3188-usb-phy"
7 "rockchip,rk3288-usb-phy"
13 register files" - phy should be a child of the GRF instead
16 Each PHY should be represented as a sub-node.
20 - #phy-cells: should be 0
21 - reg: PHY configure reg address offset in GRF
22 "0x320" - for PHY attach to OTG controller
23 "0x334" - for PHY attach to HOST0 controller
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| D | qcom-dwc3-usb-phy.txt | 1 Qualcomm DWC3 HS AND SS PHY CONTROLLER
4 DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
5 controllers. Each DWC3 PHY controller should have its own node.
9 - "qcom,dwc3-hs-usb-phy" for High Speed Synopsis PHY controller
10 - "qcom,dwc3-ss-usb-phy" for Super Speed Synopsis PHY controller
11 - reg: offset and length of the DWC3 PHY controller register set
12 - #phy-cells: must be zero
15 - clock-names: Should contain "ref" for the PHY reference clock
21 phy@100f8800 {
22 compatible = "qcom,dwc3-hs-usb-phy";
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| D | rcar-gen3-phy-usb2.txt | 1 * Renesas R-Car generation 3 USB 2.0 PHY
4 3, RZ/G1C, RZ/G2 and RZ/A2 USB 2.0 PHY contain.
7 - compatible: "renesas,usb2-phy-r7s9210" if the device is a part of an R7S9210
9 "renesas,usb2-phy-r8a77470" if the device is a part of an R8A77470
11 "renesas,usb2-phy-r8a774a1" if the device is a part of an R8A774A1
13 "renesas,usb2-phy-r8a774c0" if the device is a part of an R8A774C0
15 "renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795
17 "renesas,usb2-phy-r8a7796" if the device is a part of an R8A7796
19 "renesas,usb2-phy-r8a77965" if the device is a part of an
21 "renesas,usb2-phy-r8a77990" if the device is a part of an
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| D | meson-gxl-usb3-phy.txt | 1 * Amlogic Meson GXL and GXM USB3 PHY and OTG detection binding
4 - compatible: Should be "amlogic,meson-gxl-usb3-phy"
5 - #phys-cells: must be 0 (see phy-bindings.txt in this directory)
9 - the USB3 PHY
11 - clock-names: must contain "phy" and "peripheral"
13 - the USB3 PHY and
15 - reset-names: must contain "phy" and "peripheral"
18 - phy-supply: see phy-bindings.txt in this directory
22 usb3_phy0: phy@78080 {
23 compatible = "amlogic,meson-gxl-usb3-phy";
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| D | meson-gxl-usb2-phy.txt | 1 * Amlogic Meson GXL and GXM USB2 PHY binding
4 - compatible: Should be "amlogic,meson-gxl-usb2-phy"
6 - #phys-cells: must be 0 (see phy-bindings.txt in this directory)
9 - clocks: a phandle to the clock of this PHY
10 - clock-names: must be "phy"
11 - resets: a phandle to the reset line of this PHY
12 - reset-names: must be "phy"
13 - phy-supply: see phy-bindings.txt in this directory
17 usb2_phy0: phy@78000 {
18 compatible = "amlogic,meson-gxl-usb2-phy";
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| D | qcom-pcie2-phy.txt | 1 Qualcomm PCIe2 PHY controller
4 The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
9 "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"
11 - reg: offset and length of the PHY register set.
12 - #phy-cells: must be 0.
19 - resets: reset-specifier pairs for the "phy" and "pipe" resets
21 "phy" and "pipe"
23 - clock-output-names: name of the outgoing clock signal from the PHY PLL
27 phy@7786000 {
28 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
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| D | brcm,kona-usb2-phy.txt | 1 BROADCOM KONA USB2 PHY
4 - compatible: brcm,kona-usb2-phy
5 - reg: offset and length of the PHY registers
6 - #phy-cells: must be 0
7 Refer to phy/phy-bindings.txt for the generic PHY binding properties
11 usbphy: usb-phy@3f130000 {
12 compatible = "brcm,kona-usb2-phy";
14 #phy-cells = <0>;
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| D | brcm,brcmstb-usb-phy.txt | 1 Broadcom STB USB PHY
4 - compatible: brcm,brcmstb-usb-phy
7 registers used for general control of the PHY.
10 - #phy-cells: Shall be 1 as it expects one argument for setting
11 the type of the PHY. Possible values are:
12 - PHY_TYPE_USB2 for USB1.1/2.0 PHY
13 - PHY_TYPE_USB3 for USB3.x PHY
23 - brcm,has-xhci: Boolean indicating the phy has an XHCI phy.
24 - brcm,has-eohci: Boolean indicating the phy has an EHCI/OHCI phy.
25 - dr_mode: String, PHY Device mode.
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| D | amlogic,meson-g12a-usb2-phy.yaml | 5 $id: "http://devicetree.org/schemas/phy/amlogic,meson-g12a-usb2-phy.yaml#"
8 title: Amlogic G12A USB2 PHY
16 - amlogic,meson-g12a-usb2-phy
33 - const: phy
35 "#phy-cells":
38 phy-supply:
41 Phandle to a regulator that provides power to the PHY. This
42 regulator will be managed during the PHY power on/off sequence.
51 - "#phy-cells"
55 phy@36000 {
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| /Documentation/devicetree/bindings/ufs/ |
| D | ufs-qcom.txt | 1 * Qualcomm Technologies Inc Universal Flash Storage (UFS) PHY
3 UFSPHY nodes are defined to describe on-chip UFS PHY hardware macro.
4 Each UFS PHY node should have its own node.
6 To bind UFS PHY with UFS host controller, the controller node should
7 contain a phandle reference to UFS PHY node.
11 "qcom,ufs-phy-qmp-20nm" for 20nm ufs phy,
12 "qcom,ufs-phy-qmp-14nm" for legacy 14nm ufs phy,
13 "qcom,msm8996-ufs-phy-qmp-14nm" for 14nm ufs phy
15 - reg : should contain PHY register address space (mandatory),
18 - #phy-cells : This property shall be set to 0
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| /Documentation/devicetree/bindings/net/ |
| D | fsl-fec.txt | 7 - phy-mode : See ethernet.txt file in the same directory
10 - phy-supply : regulator that powers the Ethernet PHY.
11 - phy-handle : phandle to the PHY device connected to this device.
13 Use instead of phy-handle.
39 - mdio : specifies the mdio bus in the FEC, used as a container for phy nodes
40 according to phy.txt in the same directory
43 To avoid these, create a phy node according to phy.txt in the same
44 directory, and point the fec's "phy-handle" property to it. Then use
45 the phy's reset binding, again described by phy.txt.
46 - phy-reset-gpios : Should specify the gpio for phy reset
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