1Socionext UniPhier PCIe PHY bindings 2 3This describes the devicetree bindings for PHY interface built into 4PCIe controller implemented on Socionext UniPhier SoCs. 5 6Required properties: 7- compatible: Should contain one of the following: 8 "socionext,uniphier-ld20-pcie-phy" - for LD20 PHY 9 "socionext,uniphier-pxs3-pcie-phy" - for PXs3 PHY 10- reg: Specifies offset and length of the register set for the device. 11- #phy-cells: Must be zero. 12- clocks: A phandle to the clock gate for PCIe glue layer including 13 this phy. 14- resets: A phandle to the reset line for PCIe glue layer including 15 this phy. 16 17Optional properties: 18- socionext,syscon: A phandle to system control to set configurations 19 for phy. 20 21Refer to phy/phy-bindings.txt for the generic PHY binding properties. 22 23Example: 24 pcie_phy: phy@66038000 { 25 compatible = "socionext,uniphier-ld20-pcie-phy"; 26 reg = <0x66038000 0x4000>; 27 #phy-cells = <0>; 28 clocks = <&sys_clk 24>; 29 resets = <&sys_rst 24>; 30 socionext,syscon = <&soc_glue>; 31 }; 32