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| /Documentation/media/uapi/cec/ |
| D | cec-ioc-adap-g-phys-addr.rst | 21 CEC_ADAP_G_PHYS_ADDR, CEC_ADAP_S_PHYS_ADDR - Get or set the physical address
45 To query the current physical address applications call
47 driver stores the physical address.
49 To set a new physical address applications store the physical address in
57 To clear an existing physical address use ``CEC_PHYS_ADDR_INVALID``.
65 A :ref:`CEC_EVENT_STATE_CHANGE <CEC-EVENT-STATE-CHANGE>` event is sent when the physical address
68 The physical address is a 16-bit number where each group of 4 bits
69 represent a digit of the physical address a.b.c.d where the most
74 is supported. The physical address a device shall use is stored in the
78 different physical address of the form a.0.0.0 that the sources will
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| /Documentation/vm/ |
| D | memory-model.rst | 6 Physical Memory Model
9 Physical memory in a system may be addressed in different ways. The
10 simplest case is when the physical memory starts at address 0 and
26 All the memory models track the status of physical page frames using
30 mapping between the physical page frame number (PFN) and the
41 non-NUMA systems with contiguous, or mostly contiguous, physical
45 maps the entire physical memory. For most architectures, the holes
57 actual physical pages. In such case, the architecture specific
66 systems with physical memory starting at address different from 0.
71 The DISCONTIGMEM model treats the physical memory as a collection of
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| D | highmem.rst | 14 High memory (highmem) is used when the size of physical memory approaches or
16 impossible for the kernel to keep all of the available physical memory mapped
18 the pieces of physical memory that it wants to access.
20 The part of (physical) memory not covered by a permanent mapping is what we
40 This means that the kernel can at most map 1GiB of physical memory at any one
42 temporary maps to access the rest of the physical memory - the actual direct
56 physical pages into a contiguous virtual space. It needs global
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| /Documentation/admin-guide/mm/ |
| D | concepts.rst | 14 address to a physical address.
21 The physical memory in a computer system is a limited resource and
23 the amount of memory that can be installed. The physical memory is not
29 All this makes dealing directly with physical memory quite complex and
32 The virtual memory abstracts the details of physical memory from the
34 physical memory (demand paging) and provides a mechanism for the
40 address encoded in that instruction to a `physical` address that the
43 The physical system memory is divided into page frames, or pages. The
49 Each physical memory page can be mapped as one or more virtual
51 translation from a virtual address used by programs to the physical
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| /Documentation/ABI/testing/ |
| D | sysfs-devices-system-xen_cpu | 5 A collection of global/individual Xen physical cpu attributes
7 Individual physical cpu attributes are contained in
16 Interface to online/offline Xen physical cpus
19 to online/offline physical cpus, except cpu0 due to several
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| D | sysfs-firmware-efi | 4 Description: It shows the physical address of firmware vendor field in the
11 Description: It shows the physical address of runtime service table entry in
18 Description: It shows the physical address of config table entry in the EFI
25 Description: Displays the physical addresses of all EFI Configuration
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| D | sysfs-memory-page-offline | 6 Soft-offline the memory page containing the physical address
8 physical address of the page. The kernel will then attempt
28 Hard-offline the memory page containing the physical
30 specifying the physical address of the page. The
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| D | sysfs-class-net-grcan | 7 Hardware configuration of physical interface 0. This file reads
19 Hardware configuration of physical interface 1. This file reads
31 Configuration of which physical interface to be used. Possible
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| D | sysfs-devices-sun | 11 the slot number printed on the physical slot whenever possible."
13 So reading the sysfs file, we can identify a physical position
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| D | sysfs-kernel-vmcoreinfo | 8 Shows physical address and size of vmcoreinfo ELF note.
9 First value contains physical address of note in hex and
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| /Documentation/ |
| D | bus-virt-phys-mapping.txt | 21 controller the physical address of the buffers, which is correct on x86
22 (because all bus master devices see the physical memory mappings directly).
31 - CPU untranslated. This is the "physical" address. Physical address
45 Now, on normal PCs the bus address is exactly the same as the physical
58 the viewpoint of the devices, you have the reverse, and the physical memory
61 So when the CPU wants any bus master to write to physical memory 0, it
67 physical address: 0
76 physical address: 0
80 (but there are also Alphas where the physical address and the bus address
125 And you generally **never** want to use the physical address, because you can't
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| D | debugging-via-ohci1394.txt | 2 Using physical DMA provided by OHCI-1394 FireWire controllers for debugging
11 a "Physical Response Unit" which executes specific requests by employing
16 physical system memory and, for read requests, send the result of
17 the physical memory read back to the requester.
26 of physical address space. This can be a problem on IA64 machines where
31 physical addresses above 4 GB, but this feature is currently not enabled by
43 The firewire-ohci driver in drivers/firewire uses filtered physical
45 Pass the remote_dma=1 parameter to the driver to get unfiltered physical DMA.
81 disable all physical DMA on each bus reset.
107 controller implements a writable Physical Upper Bound register. This is
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| /Documentation/xtensa/ |
| D | booting.rst | 12 address must be the physical address.
19 virtual or physical address. In either case it must be within the default
20 virtual mapping. It is considered physical if it is within the range of
21 physical addresses covered by the default KSEG mapping (XCHAL_KSEG_PADDR..
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| /Documentation/arm/ |
| D | porting.rst | 12 virtual address to a physical address. Normally, it is simply:
22 virtual or physical addresses here, since the MMU will be off at
43 Physical address to place the initial RAM disk. Only relevant if
54 Physical address of the struct param_struct or tag list, giving the
62 Physical start address of the first bank of RAM.
66 boot phase, virtual address PAGE_OFFSET will be mapped to physical
113 `pram` specifies the physical start address of RAM. Must always
116 `pio` is the physical address of an 8MB region containing IO for
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| /Documentation/driver-api/ |
| D | lightnvm-pblk.rst | 1 pblk: Physical Block Device Target
7 - Map logical addresses onto physical addresses (4KB granularity) in a
8 logical-to-physical (L2P) table.
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| /Documentation/devicetree/bindings/display/ |
| D | brcm,bcm-vc4.txt | 13 - reg: Physical base address and length of the PV's registers
19 - reg: Physical base address and length of the HVS's registers
25 - reg: Physical base address and length of the two register ranges
43 - reg: Physical base address and length of the registers
51 - reg: Physical base address and length of the registers
58 - reg: Physical base address and length of the V3D's registers
67 - reg: Physical base address and length of the DSI block's registers
79 - reg: Physical base address and length of the TXP block's registers
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| /Documentation/admin-guide/kdump/ |
| D | vmcoreinfo.rst | 53 virtual to physical addresses.
60 direct kernel map to a physical address.
71 Physical addresses are translated to struct pages by treating them as
72 an index into the mem_map array. Right-shifting a physical address
270 corresponding physical address.
276 to physical addresses. The init_top_pgt is somewhat similar to
315 mask. This is used to remove the SME mask and obtain the true physical
333 Denotes whether physical address extensions are enabled. It has the cost
336 crash kernel when converting virtual addresses to physical addresses.
380 The offset between the kernel virtual and physical mappings. Used to
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| /Documentation/devicetree/bindings/misc/ |
| D | nvidia,tegra186-misc.txt | 9 - reg: Should contain 2 entries: The first entry gives the physical address
11 features. The second entry specifies the physical address and length
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| /Documentation/scsi/ |
| D | scsi_fc_transport.txt | 35 New FC standards have defined mechanisms which allows for a single physical
40 physical link to the switch for communication. Each N_Port_ID can have a
56 The fc_host associated with the physical adapter will export the ability
61 Thus, whether a FC port is based on a physical port or on a virtual port,
83 object corresponding to the physical adapter. The LLDD will allocate
89 device tree. If the vport's parent is not the physical port's scsi_host,
90 a symbolic link to the vport object will be placed in the physical
94 The typical Physical Port's Scsi_Host:
98 and then the vport is created on the Physical Port:
107 /sys/class/scsi_host/host17 physical port's scsi_host
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| /Documentation/devicetree/bindings/mfd/ |
| D | mfd.txt | 11 drivers, level shifters, PHY (physical interfaces to things like USB or
29 the child's base address to 0, the physical address within parent's address
32 - #address-cells: Specifies the number of cells used to represent physical base
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| /Documentation/s390/ |
| D | vfio-ccw.rst | 89 physical addresses).
91 - Host kernel translates the guest physical addresses to real addresses
99 Physical vfio ccw device and its child mdev
104 Channel I/O does not have IOMMU hardware support, so the physical
115 - The vfio_ccw driver for the physical subchannel device.
118 parent (physical) device. As a consequence, mdev provides vfio_ccw a
136 means that a device programmed in a VM with guest physical addresses
138 address, pin the page and program the hardware with the host physical
144 backend for the physical devices to pin and unpin pages by demand.
160 | |Physical | +<-----------------------+ |
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| /Documentation/devicetree/bindings/display/tegra/ |
| D | nvidia,tegra20-host1x.txt | 5 - reg: Physical base address and length of the controller's registers.
11 - #address-cells: The number of cells used to represent physical base addresses
30 - reg: Physical base address and length of the controller's registers.
43 - reg: Physical base address and length of the controller's registers.
56 - reg: Physical base address and length of the controller's registers.
69 - reg: Physical base address and length of the controller's registers.
82 - reg: Physical base address and length of the controller's registers.
95 - reg: Physical base address and length of the controller's registers.
113 - reg: Physical base address and length of the controller's registers.
141 - reg: Physical base address and length of the controller's registers.
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| /Documentation/devicetree/bindings/media/ |
| D | qcom,camss.txt | 126 Definition: The physical clock lane index. On 8916
127 the value must always be <1> as the physical
131 D-PHY physical clock lane is labeled as 7.
135 Definition: An array of physical data lanes indexes.
138 indicates physical lane index. Lane swapping
139 is supported. Physical lane indexes for
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| /Documentation/devicetree/bindings/gpio/ |
| D | nvidia,tegra186-gpio.txt | 15 register set. These registers exist in a single contiguous block of physical
25 controllers, these registers are exposed via multiple "physical aliases" in
28 just one of these physical aliases.
78 a) The single physical alias that this OS should use.
79 b) All physical aliases that exist in the controller. This is
81 the physical aliases.
86 Array of (physical base address, length) tuples.
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| /Documentation/devicetree/bindings/usb/ |
| D | ohci-nxp.txt | 5 - reg: physical base address of the controller and length of memory mapped
9 the UDC controller for connecting to the USB physical layer
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