Searched full:resets (Results 1 – 25 of 354) sorted by relevance
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| /Documentation/devicetree/bindings/phy/ |
| D | phy-hisi-inno-usb2.txt | 11 - resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
23 - resets: The phandle and reset specifier pair for PHY port reset signal.
40 resets = <&crg 0xbc 4>;
47 resets = <&crg 0xbc 8>;
53 resets = <&crg 0xbc 9>;
61 resets = <&crg 0xbc 6>;
68 resets = <&crg 0xbc 10>;
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| D | qcom-pcie2-phy.txt | 19 - resets: reset-specifier pairs for the "phy" and "pipe" resets
20 - reset-names: list of resets, should contain:
32 resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
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| D | phy-cadence-sierra.txt | 9 - resets: Must contain an entry for each in reset-names.
34 - resets: Must contain one entry which controls the reset line for the
48 resets = <&phyrst 0>, <&phyrst 1>;
56 resets = <&phyrst 2>;
63 resets = <&phyrst 4>;
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| D | allwinner,sun6i-a31-mipi-dphy.yaml | 33 resets:
42 - resets
53 resets = <&ccu 4>;
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| D | amlogic,meson-g12a-usb3-pcie-phy.yaml | 28 resets:
43 - resets
54 resets = <&phy_reset>;
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| D | amlogic,meson-g12a-usb2-phy.yaml | 28 resets:
49 - resets
60 resets = <&phy_reset>;
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| D | qcom,usb-hs-phy.txt | 32 - resets:
35 Definition: Should contain the phy and POR resets
40 Definition: Should contain "phy" and "por" for the phy and POR resets
76 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
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| D | sun9i-usb-phy.txt | 15 - resets : a list of phandle + reset specifier pairs
24 It is recommended to list all clocks and resets available.
34 resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>;
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| D | berlin-usb-phy.txt | 7 - resets: reference to the reset controller
15 resets = <&chip 0x104 14>;
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| D | phy-ath79-usb.txt | 7 - resets: references to the reset controllers
15 resets = <&rst 4>, <&rst 3>;
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| /Documentation/devicetree/bindings/fpga/ |
| D | altera-hps2fpga-bridge.txt | 9 - resets : Phandle and reset specifier for this bridge's reset
18 resets = <&rst LWHPS2FPGA_RESET>;
26 resets = <&rst HPS2FPGA_RESET>;
34 resets = <&rst FPGA2HPS_RESET>;
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| /Documentation/devicetree/bindings/display/tegra/ |
| D | nvidia,tegra20-host1x.txt | 18 - resets: Must contain an entry for each entry in reset-names.
34 - resets: Must contain an entry for each entry in reset-names.
47 - resets: Must contain an entry for each entry in reset-names.
60 - resets: Must contain an entry for each entry in reset-names.
73 - resets: Must contain an entry for each entry in reset-names.
86 - resets: Must contain an entry for each entry in reset-names.
103 - resets: Must contain an entry for each entry in reset-names.
121 - resets: Must contain an entry for each entry in reset-names.
152 - resets: Must contain an entry for each entry in reset-names.
184 - resets: Must contain an entry for each entry in reset-names.
[all …]
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| /Documentation/devicetree/bindings/regulator/ |
| D | uniphier-regulator.txt | 10 the regulator, it is necessary to control the clocks and resets to enable
11 this layer. These clocks and resets should be described in each property.
26 - resets: A list of phandles to the reset control for USB3 glue layer.
27 According to the reset-names, appropriate resets are required.
50 resets = <&sys_rst 14>;
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| /Documentation/devicetree/bindings/display/ |
| D | st,stih4xx.txt | 38 - resets: resets to be used by the device
40 - reset-names: names of the resets listed in resets property in the same
51 - resets: resets to be used by the device
53 - reset-names: names of the resets listed in resets property in the same
111 - resets: resets to be used by the device
113 - reset-names: names of the resets listed in resets property in the same
187 resets = <&softreset STIH416_COMPO_M_SOFTRESET>, <&softreset STIH416_COMPO_A_SOFTRESET>;
196 resets = <&softreset STIH416_HDTVOUT_SOFTRESET>;
236 resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
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| /Documentation/devicetree/bindings/net/ |
| D | mediatek,mt7620-gsw.txt | 10 - resets: Should contain the gigabit switches resets
19 resets = <&rstctrl 23>;
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| D | ralink,rt3050-esw.txt | 11 - resets: Should contain the embedded switches resets
25 resets = <&rstctrl 23>;
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| D | allwinner,sun8i-a83t-emac.yaml | 53 - resets
160 resets:
165 - resets
195 resets = <&ccu 12>;
226 resets = <&ccu 39>;
246 resets = <&ccu 12>;
276 resets = <&ccu 39>;
299 resets = <&ccu 13>;
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| /Documentation/devicetree/bindings/reset/ |
| D | img,pistachio-reset.txt | 40 Device nodes should specify the reset channel required in their "resets"
49 resets = <&pistachio_reset PISTACHIO_RESET_SPDIF_OUT>;
54 Macro definitions for the supported resets can be found in:
55 include/dt-bindings/reset/pistachio-resets.h
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| D | xlnx,zynqmp-reset.txt | 4 The Zynq UltraScale+ MPSoC has several different resets.
7 about zynqmp resets.
41 <dt-bindings/reset/xlnx-zynqmp-resets.h>
48 resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
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| D | st,sti-powerdown.txt | 33 Device nodes should specify the reset channel required in their "resets"
40 resets = <&powerdown STIH407_USB3_POWERDOWN>,
45 include/dt-bindings/reset/stih407-resets.h
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| /Documentation/devicetree/bindings/i2c/ |
| D | allwinner,sun6i-a31-p2wi.yaml | 29 resets:
41 - resets
55 resets = <&apb0_rst 3>;
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| /Documentation/devicetree/bindings/dma/ |
| D | allwinner,sun6i-a31-dma.yaml | 38 resets:
47 - resets
58 resets = <&ahb1_rst 6>;
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| /Documentation/devicetree/bindings/bus/ |
| D | allwinner,sun8i-a23-rsb.yaml | 36 resets:
58 - resets
68 resets = <&apb0_rst 3>;
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| /Documentation/devicetree/bindings/crypto/ |
| D | st,stm32-cryp.txt | 10 - resets: The input reset of the CRYP instance
18 resets = <&rcc STM32F7_AHB2_RESET(CRYP)>;
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | lantiq-gswip.txt | 37 - resets : list of resets of the embedded GPHY
38 - reset-names : list of names of the resets
132 resets = <&reset0 31 30>;
139 resets = <&reset0 29 28>;
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