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/Documentation/devicetree/bindings/iommu/
Dqcom,iommu.txt3 Qualcomm "B" family devices which are not compatible with arm-smmu have
4 a similar looking IOMMU but without access to the global register space,
6 to non-secure vs secure interrupt line.
10 - compatible : Should be one of:
12 "qcom,msm8916-iommu"
14 Followed by "qcom,msm-iommu-v1".
16 - clock-names : Should be a pair of "iface" (required for IOMMUs
17 register group access) and "bus" (required for
18 the IOMMUs underlying bus access).
20 - clocks : Phandles for respective clocks described by
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Dmsm,iommu-v0.txt5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9 - compatible: Must contain "qcom,apq8064-iommu".
10 - reg: Base address and size of the IOMMU registers.
11 - interrupts: Specifiers for the MMU fault interrupts. For instances that
12 support secure mode two interrupts must be specified, for non-secure and
13 secure mode, in that order. For instances that don't support secure mode a
15 - #iommu-cells: The number of cells needed to specify the stream id. This
17 - qcom,ncb: The total number of context banks in the IOMMU.
18 - clocks : List of clocks to be used during SMMU register access. See
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
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Darm,smmu.txt12 - compatible : Should be one of:
14 "arm,smmu-v1"
15 "arm,smmu-v2"
16 "arm,mmu-400"
17 "arm,mmu-401"
18 "arm,mmu-500"
19 "cavium,smmu-v2"
20 "qcom,smmu-v2"
25 Qcom SoCs must contain, as below, SoC-specific compatibles
26 along with "qcom,smmu-v2":
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Darm,smmu-v3.txt4 revisions, replacing the MMIO register interface with in-memory command
10 - compatible : Should include:
12 * "arm,smmu-v3" for any SMMUv3 compliant
16 - reg : Base address and size of the SMMU.
18 - interrupts : Non-secure interrupt list describing the wired
20 interrupt-names. If no wired interrupts are
23 - interrupt-names : When the interrupts property is present, should
25 * "eventq" - Event Queue not empty
26 * "priq" - PRI Queue not empty
27 * "cmdq-sync" - CMD_SYNC complete
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/Documentation/devicetree/bindings/arm/
Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - arm,armv8-pmuv3
24 - arm,cortex-a73-pmu
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Dcci.txt5 ARM multi-cluster systems maintain intra-cluster coherency through a
24 - compatible
28 "arm,cci-400"
29 "arm,cci-500"
30 "arm,cci-550"
32 - reg
40 - ranges:
53 - CCI control interface nodes
55 Node name must be "slave-if".
61 - compatible
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Darm,scmi.txt2 ----------------------------------------------------------
17 - compatible : shall be "arm,scmi"
18 - mboxes: List of phandle and mailbox channel specifiers. It should contain
22 - shmem : List of phandle pointing to the shared memory(SHM) area as per
24 - #address-cells : should be '1' if the device has sub-nodes, maps to
25 protocol identifier for a given sub-node.
26 - #size-cells : should be '0' as 'reg' property doesn't have any size
31 - mbox-names: shall be "tx" or "rx" depending on mboxes entries.
40 Each protocol supported shall have a sub-node with corresponding compatible
43 mboxes, mbox-names and shmem shall be present in the sub-node corresponding
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Darm,scpi.txt2 ----------------------------------------------------------
10 - compatible : should be
12 * "arm,scpi-pre-1.0" : For implementations complying to all
14 - mboxes: List of phandle and mailbox channel specifiers
17 - shmem : List of phandle pointing to the shared memory(SHM) area between the
27 ------------------------------------------------------------
34 - compatible : should be "arm,scpi-clocks"
36 protocol much be listed as sub-nodes under this node.
38 Sub-nodes
41 - compatible : shall include one of the following
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/Documentation/devicetree/bindings/interrupt-controller/
Dmarvell,icu.txt2 --------------------------------
5 responsible for collecting all wired-interrupt sources in the CP and
8 These messages will access a different GIC memory area depending on
13 - compatible: Should be "marvell,cp110-icu"
15 - reg: Should contain ICU registers location and length.
22 - compatible: Should be one of:
23 * "marvell,cp110-icu-nsr"
24 * "marvell,cp110-icu-sr"
25 * "marvell,cp110-icu-sei"
26 * "marvell,cp110-icu-rei"
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/Documentation/driver-api/
Dvfio.rst2 VFIO - "Virtual Function I/O" [1]_
7 allotted. This includes x86 hardware with AMD-Vi and Intel VT-d,
10 agnostic framework for exposing direct device access to userspace, in
11 a secure, IOMMU protected environment. In other words, this allows
12 safe [2]_, non-privileged, userspace drivers.
15 access ("device assignment") when configured for the highest possible
19 bare-metal device drivers [3]_.
22 field, also benefit from low-overhead, direct device access from
23 userspace. Examples include network adapters (often non-TCP/IP based)
28 and requires root privileges to access things like PCI configuration
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/Documentation/devicetree/bindings/edac/
Dsocfpga-eccmgr.txt8 - compatible : Should be "altr,socfpga-ecc-manager"
9 - #address-cells: must be 1
10 - #size-cells: must be 1
11 - ranges : standard definition, should translate from local addresses
17 - compatible : Should be "altr,socfpga-l2-ecc"
18 - reg : Address and size for ECC error interrupt clear registers.
19 - interrupts : Should be single bit error interrupt, then double bit error
24 - compatible : Should be "altr,socfpga-ocram-ecc"
25 - reg : Address and size for ECC error interrupt clear registers.
26 - iram : phandle to On-Chip RAM definition.
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/Documentation/networking/
Dfilter.txt5 ------------
12 BPF allows a user-space program to attach a filter onto any socket and
37 The biggest user of this construct might be libpcap. Issuing a high-level
38 filter command like `tcpdump -i em1 port 22` passes through the libpcap
40 via SO_ATTACH_FILTER to the kernel. `tcpdump -i em1 port 22 -ddd`
45 qdisc layer, SECCOMP-BPF (SECure COMPuting [1]), and lots of other places
48 [1] Documentation/userspace-api/seccomp_filter.rst
53 architecture for user-level packet capture. In Proceedings of the
56 CA, USA, 2-2. [http://www.tcpdump.org/papers/bpf-usenix93.pdf]
59 ---------
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/Documentation/virt/kvm/
Dapi.txt1 The Definitive KVM (Kernel-based Virtual Machine) API Documentation
5 ----------------------
10 - System ioctls: These query and set global attributes which affect the
14 - VM ioctls: These query and set attributes that affect an entire virtual
21 - vcpu ioctls: These query and set attributes that control the operation
29 - device ioctls: These query and set attributes that control the operation
36 -------------------
73 -------------
77 facility that allows backward-compatible extensions to the API to be
87 ------------------
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/Documentation/admin-guide/
Dkernel-parameters.txt5 force -- enable ACPI if default was off
6 on -- enable ACPI but allow fallback to DT [arm64]
7 off -- disable ACPI if default was on
8 noirq -- do not use ACPI for IRQ routing
9 strict -- Be less tolerant of platforms that are not
11 rsdt -- prefer RSDT over (default) XSDT
12 copy_dsdt -- copy DSDT to memory
56 Documentation/firmware-guide/acpi/debug.rst for more information about
80 strict (default): access to resources claimed by ACPI
81 is denied; legacy drivers trying to access reserved
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