Searched full:shall (Results 1 – 25 of 427) sorted by relevance
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| /Documentation/devicetree/bindings/clock/ |
| D | qcom,gpucc.txt | 5 - compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc"
6 - reg : shall contain base register location and length
7 - #clock-cells : from common clock binding, shall contain 1
8 - #reset-cells : from common reset binding, shall contain 1
9 - #power-domain-cells : from generic power domain binding, shall contain 1
10 - clocks : shall contain the XO clock
11 shall contain the gpll0 out main clock (msm8998)
12 - clock-names : shall be "xo"
13 shall be "gpll0" (msm8998)
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| D | vt8500.txt | 8 - compatible : shall be one of the following:
16 - reg : shall be the control register offset from PMC base for the pll clock.
17 - clocks : shall be the input parent clock phandle for the clock. This should
19 - #clock-cells : from common clock binding; shall be set to 0.
22 - clocks : shall be the input parent clock phandle for the clock. This should
24 - #clock-cells : from common clock binding; shall be set to 0.
36 - enable-reg : shall be the register offset from PMC base for the enable
38 - enable-bit : shall be the bit within enable-reg to enable/disable the clock.
44 - divisor-reg : shall be the register offset from PMC base for the divisor
47 - divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f
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| D | xgene.txt | 8 - compatible : shall be one of the following:
17 - reg : shall be the physical PLL register address for the pll clock.
18 - clocks : shall be the input parent clock phandle for the clock. This should
20 - #clock-cells : shall be set to 1.
21 - clock-output-names : shall be the name of the PLL referenced by derive
24 - clock-names : shall be the name of the PLL. If missing, use the device name.
27 - reg : shall be the physical register address for the pmd clock.
28 - clocks : shall be the input parent clock phandle for the clock.
29 - #clock-cells : shall be set to 1.
30 - clock-output-names : shall be the name of the clock referenced by derive
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| D | qcom,videocc.txt | 5 - compatible : shall contain "qcom,sdm845-videocc"
6 - reg : shall contain base register location and length
7 - #clock-cells : from common clock binding, shall contain 1.
8 - #power-domain-cells : from generic power domain binding, shall contain 1.
9 - #reset-cells : from common reset binding, shall contain 1.
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| D | qcom,dispcc.txt | 6 - compatible : shall contain "qcom,sdm845-dispcc"
7 - reg : shall contain base register location and length.
8 - #clock-cells : from common clock binding, shall contain 1.
9 - #reset-cells : from common reset binding, shall contain 1.
10 - #power-domain-cells : from generic power domain binding, shall contain 1.
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| D | qcom,camcc.txt | 5 - compatible : shall contain "qcom,sdm845-camcc".
6 - reg : shall contain base register location and length.
7 - #clock-cells : from common clock binding, shall contain 1.
8 - #reset-cells : from common reset binding, shall contain 1.
9 - #power-domain-cells : from generic power domain binding, shall contain 1.
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| D | qcom,mmcc.txt | 5 - compatible : shall contain only one of the following:
14 - reg : shall contain base register location and length
15 - #clock-cells : shall contain 1
16 - #reset-cells : shall contain 1
19 - #power-domain-cells : shall contain 1
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| D | ti,cdce706.txt | 7 - compatible: shall be "ti,cdce706".
8 - reg: i2c device address, shall be in range [0x68...0x6b].
9 - #clock-cells: from common clock binding; shall be set to 1.
11 handles, shall be reference clock(s) connected to CLK_IN0
13 - clock-names: shall be clk_in0 and/or clk_in1. Use clk_in0
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| D | qcom,lcc.txt | 5 - compatible : shall contain only one of the following:
12 - reg : shall contain base register location and length
13 - #clock-cells : shall contain 1
14 - #reset-cells : shall contain 1
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| D | microchip,pic32.txt | 10 - compatible: shall be "microchip,pic32mzda-clk".
11 - reg: shall contain base address and length of clock registers.
12 - #clock-cells: shall be 1.
15 - microchip,pic32mzda-sosc: shall be added only if platform has
28 The clock consumer shall specify the desired clock-output of the clock
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| D | at91-clock.txt | 10 - compatible : shall be one of the following:
16 - #clock-cells : shall be 1 for "microchip,sam9x60-sckc" otherwise shall be 0.
17 - clocks : shall be the input parent clock phandle for the clock.
34 - compatible : shall be "atmel,<chip>-pmc", "syscon" or
40 - #clock-cells : from common clock binding; shall be set to 2. The first entry
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| D | calxeda.txt | 8 - compatible : shall be one of the following:
14 - reg : shall be the control register offset from SYSREGs base for the clock.
15 - clocks : shall be the input parent clock phandle for the clock. This is
17 - #clock-cells : from common clock binding; shall be set to 0.
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| D | qcom,turingcc.txt | 5 - compatible: shall contain "qcom,qcs404-turingcc".
6 - reg: shall contain base register location and length.
8 - #clock-cells: from common clock binding, shall contain 1.
9 - #reset-cells: from common reset binding, shall contain 1.
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| D | silabs,si5351.txt | 15 - compatible: shall be one of the following:
20 - reg: i2c device address, shall be 0x60 or 0x61.
21 - #clock-cells: from common clock binding; shall be set to 1.
23 handles, shall be xtal reference clock or xtal and clkin for
26 - #address-cells: shall be set to 1.
27 - #size-cells: shall be set to 0.
43 - silabs,clock-source: source clock of the output divider stage N, shall be
48 - silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}.
53 - silabs,disable-state : clock output disable state, shall be
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| /Documentation/devicetree/bindings/clock/ti/davinci/ |
| D | da8xx-cfgchip.txt | 13 - compatible: shall be "ti,da830-usb-phy-clocks".
14 - #clock-cells: from common clock binding; shall be set to 1.
16 - clock-names: shall be "fck", "usb_refclkin", "auxclk"
24 - compatible: shall be "ti,da830-tbclksync".
25 - #clock-cells: from common clock binding; shall be set to 0.
27 - clock-names: shall be "fck"
32 - compatible: shall be "ti,da830-div4p5ena".
33 - #clock-cells: from common clock binding; shall be set to 0.
35 - clock-names: shall be "pll0_pllout"
40 - compatible: shall be "ti,da850-async1-clksrc".
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| D | pll.txt | 8 - compatible: shall be one of:
14 - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
15 - for "ti,da850-pll1", shall be "clksrc"
30 - #clock-cells: shall be 0
38 - #clock-cells: shall be 1
45 - #clock-cells: shall be 0
51 - #clock-cells: shall be 0
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| D | psc.txt | 7 - compatible: shall be one of:
11 - #clock-cells: from common clock binding; shall be set to 1
12 - #power-domain-cells: from generic power domain binding; shall be set to 1.
15 - for "ti,da850-psc0", shall be "pll0_sysclk1", "pll0_sysclk2",
17 - for "ti,da850-psc1", shall be "pll0_sysclk2", "pll0_sysclk4", "async3"
20 - #reset-cells: from reset binding; shall be set to 1 - only applicable when
25 Clock, power domain and reset consumers shall use the local power domain
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | open-pic.txt | 14 shall be <string> and the value shall include "open-pic".
17 PIC's addressable register space. The type shall be <prop-encoded-array>.
20 as an Open PIC. No property value shall be defined.
23 interrupt source. The type shall be a <u32> and the value shall be 2.
26 address. The type shall be <u32> and the value shall be 0. As such,
32 shall not be reset during runtime initialization. No property value shall
34 initialization related to interrupt sources shall be limited to sources
74 // The PIC shall not be reset.
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| D | img,meta-intc.txt | 9 The type shall be <string> and the value shall include "img,meta-intc".
15 as an interrupt controller. No property value shall be defined.
18 interrupt source. The type shall be a <u32> and the value shall be 2.
21 address. The type shall be <u32> and the value shall be 0. As such,
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| D | img,pdc-intc.txt | 11 The type shall be <string> and the value shall include "img,pdc-intc".
14 addressable register space. The type shall be <prop-encoded-array>.
17 as an interrupt controller. No property value shall be defined.
20 interrupt source. The type shall be a <u32> and the value shall be 2.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
27 shared SysWake interrupt, and remaining specifies shall be PDC peripheral
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| /Documentation/devicetree/bindings/usb/ |
| D | usb-device.txt | 12 A combined node shall be used instead of a device node and an interface node
22 The textual representation of VID and PID shall be in lower case hexadecimal
31 - #address-cells: shall be 2
32 - #size-cells: shall be 0
38 number. The textual representation of VID, PID, CN and IN shall be in lower
51 The textual representation of VID and PID shall be in lower case hexadecimal
60 - #address-cells: shall be 1
61 - #size-cells: shall be 0
65 - #address-cells: shall be 1
66 - #size-cells: shall be 0
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| /Documentation/devicetree/bindings/edac/ |
| D | apm-xgene-edac.txt | 14 - compatible : Shall be "apm,xgene-edac".
23 - reg : First resource shall be the CPU bus (PCP) resource.
28 - compatible : Shall be "apm,xgene-edac-mc".
29 - reg : First resource shall be the memory controller unit
34 - compatible : Shall be "apm,xgene-edac-pmd" or
36 - reg : First resource shall be the PMD resource.
40 - compatible : Shall be "apm,xgene-edac-l3" or
42 - reg : First resource shall be the L3 EDAC resource.
45 - compatible : Shall be "apm,xgene-edac-soc-v1" for revision 1 or
48 - reg : First resource shall be the SoC EDAC resource.
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| /Documentation/devicetree/bindings/perf/ |
| D | apm-xgene-pmu.txt | 14 - compatible : Shall be "apm,xgene-pmu" for revision 1 or
19 - reg : First resource shall be the CPU bus PMU resource.
23 - compatible : Shall be "apm,xgene-pmu-l3c".
24 - reg : First resource shall be the L3C PMU resource.
27 - compatible : Shall be "apm,xgene-pmu-iob".
28 - reg : First resource shall be the IOB PMU resource.
31 - compatible : Shall be "apm,xgene-pmu-mcb".
32 - reg : First resource shall be the MCB PMU resource.
36 - compatible : Shall be "apm,xgene-pmu-mc".
37 - reg : First resource shall be the MC PMU resource.
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| /Documentation/devicetree/bindings/ata/ |
| D | apm-xgene.txt | 7 - compatible : Shall contain:
9 - reg : First memory resource shall be the AHCI memory
11 Second memory resource shall be the host controller
13 Third memory resource shall be the host controller
15 4th memory resource shall be the host controller
17 5th optional memory resource shall be the host
28 - status : Shall be "ok" if enabled or "disabled" if disabled.
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| /Documentation/devicetree/bindings/i3c/ |
| D | cdns,i3c-master.txt | 6 - compatible: shall be "cdns,i3c-master"
7 - clocks: shall reference the pclk and sysclk
8 - clock-names: shall contain "pclk" and "sysclk"
15 - #address-cells: shall be set to 1
16 - #size-cells: shall be set to 0
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