| /Documentation/devicetree/bindings/bus/ |
| D | simple-pm-bus.txt | 1 Simple Power-Managed Bus
4 A Simple Power-Managed Bus is a transparent bus that doesn't need a real
7 However, its bus controller is part of a PM domain, or under the control of a
8 functional clock. Hence, the bus controller's PM domain and/or clock must be
9 enabled for child devices connected to the bus (either on-SoC or externally)
12 While "simple-pm-bus" follows the "simple-bus" set of properties, as specified
13 in the Devicetree Specification, it is not an extension of "simple-bus".
17 - compatible: Must contain at least "simple-pm-bus".
18 Must not contain "simple-bus".
20 vendor-specific compatible values.
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| D | renesas,bsc.txt | 1 Renesas Bus State Controller (BSC)
4 The Renesas Bus State Controller (BSC, sometimes called "LBSC within Bus
5 Bridge", or "External Bus Interface") can be found in several Renesas ARM SoCs.
6 It provides an external bus for connecting multiple external devices to the
9 While the BSC is a fairly simple memory-mapped bus, it may be part of a PM
15 The bindings for the BSC extend the bindings for "simple-pm-bus".
19 - compatible: Must contain an SoC-specific value, and "renesas,bsc" and
20 "simple-pm-bus" as fallbacks.
21 SoC-specific values can be:
22 "renesas,bsc-r8a73a4" for R-Mobile APE6 (r8a73a4)
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| D | mvebu-mbus.txt | 6 - compatible: Should be set to one of the following:
7 marvell,armada370-mbus
8 marvell,armadaxp-mbus
9 marvell,armada375-mbus
10 marvell,armada380-mbus
11 marvell,kirkwood-mbus
12 marvell,dove-mbus
13 marvell,orion5x-88f5281-mbus
14 marvell,orion5x-88f5182-mbus
15 marvell,orion5x-88f5181-mbus
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| D | nvidia,tegra20-gmi.txt | 1 Device tree bindings for NVIDIA Tegra Generic Memory Interface bus
3 The Generic Memory Interface bus enables memory transfers between internal and
10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
17 - reset-names : Must include the following entries: "gmi"
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| D | uniphier-system-bus.txt | 1 UniPhier System Bus
3 The UniPhier System Bus is an external bus that connects on-board devices to
4 the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
7 Before any access to the bus, the bus controller must be configured; the bus
9 within each bank to the CPU-viewed address. The needed setup includes the base
11 optimized for faster bus access.
14 - compatible: should be "socionext,uniphier-system-bus".
15 - reg: offset and length of the register set for the bus controller device.
16 - #address-cells: should be 2. The first cell is the bank number (chip select).
18 - #size-cells: should be 1.
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| /Documentation/devicetree/bindings/mfd/ |
| D | mfd.txt | 1 Multi-Function Devices (MFD)
4 more than one non-unique yet varying hardware functionality.
8 - A mixed signal ASIC on an external bus, sometimes a PMIC (Power Management
14 - A range of memory registers containing "miscellaneous system registers" also
20 - compatible : "simple-mfd" - this signifies that the operating system should
22 "simple-bus" indicates when to see subnodes as children for a simple
23 memory-mapped bus. For more complex devices, when the nexus driver has to
28 - ranges: Describes the address mapping relationship to the parent. Should set
32 - #address-cells: Specifies the number of cells used to represent physical base
35 - #size-cells: Specifies the number of cells used to represent the size of an
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| D | aspeed-lpc.txt | 2 Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
5 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
6 peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
7 primary use case of the Aspeed LPC controller is as a slave on the bus
9 conditions it can also take the role of bus master.
11 The LPC controller is represented as a multi-function device to account for the
24 APB-to-LPC bridging amonst other functions.
27 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
28 management and bus snoop configuration.
39 [1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c888374547021…
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| /Documentation/devicetree/bindings/net/ |
| D | marvell,prestera.txt | 2 -------------------------------------
5 - compatible: must be "marvell,prestera" and one of the following
6 "marvell,prestera-98dx3236",
7 "marvell,prestera-98dx3336",
8 "marvell,prestera-98dx4251",
9 - reg: address and length of the register set for the device.
10 - interrupts: interrupt for the device
13 - dfx: phandle reference to the "DFX Server" node
18 compatible = "simple-bus";
19 #address-cells = <1>;
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| /Documentation/devicetree/bindings/c6x/ |
| D | soc.txt | 1 C6X System-on-Chip
2 ------------------
6 - compatible: "simple-bus"
7 - #address-cells: must be 1
8 - #size-cells: must be 1
9 - ranges
13 - model: specific SoC model
15 - nodes for IP blocks within SoC
21 compatible = "simple-bus";
23 #address-cells = <1>;
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| D | emifa.txt | 2 -------------------------
4 The emifa node describes a simple external bus controller found on some C6X
9 - compatible: must be "ti,c64x+emifa", "simple-bus"
10 - reg: register area base and size
11 - #address-cells: must be 2 (chip-select + offset)
12 - #size-cells: must be 1
13 - ranges: mapping from EMIFA space to parent space
18 - ti,dscr-dev-enable: Device ID if EMIF is enabled/disabled from DSCR
20 - ti,emifa-burst-priority:
26 - ti,emifa-ce-config:
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| /Documentation/devicetree/bindings/arm/stm32/ |
| D | mlahb.txt | 1 ML-AHB interconnect bindings
3 These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
4 a Cortex-M subsystem with dedicated memories.
7 Cortex-M firmware accesses among those ports allows to tune the system
14 - compatible: should be "simple-bus"
15 - dma-ranges: describes memory addresses translation between the local CPU and
16 the remote Cortex-M processor. Each memory region, is declared with
18 - param 1: device base address (Cortex-M processor address)
19 - param 2: physical base address (local CPU address)
20 - param 3: size of the memory region.
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| /Documentation/devicetree/bindings/arm/ |
| D | arm-boards | 2 -----------------------------------------------------------------------------
3 ARM's oldest Linux-supported platform with connectors for different core
7 compatible = "arm,integrator-ap"; /* Application Platform */
8 compatible = "arm,integrator-cp"; /* Compact Platform */
10 FPGA type interrupt controllers, see the versatile-fpga-irq binding doc.
14 - core-module: the root node to the Integrator platforms must have
15 a core-module with regs and the compatible string
16 "arm,core-module-integrator"
17 - external-bus-interface: the root node to the Integrator platforms
18 must have an external bus interface with regs and the
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| D | gemini.txt | 3 The Gemini SoC is the project name for an ARMv4 FA525-based SoC originally
20 - soc: the SoC should be represented by a simple bus encompassing all the
21 onchip devices, this is referred to as the soc bus node.
23 - syscon: the soc bus node must have a system controller node pointing to the
25 "cortina,gemini-syscon", "syscon";
28 - reg: syscon register location and size.
29 - #clock-cells: should be set to <1> - the system controller is also a
31 - #reset-cells: should be set to <1> - the system controller is also a
35 <dt-bindings/clock/cortina,gemini-clock.h>
38 <dt-bindings/reset/cortina,gemini-reset.h>
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-pci-devices-cciss | 1 What: /sys/bus/pci/devices/<dev>/ccissX/cXdY/model
8 What: /sys/bus/pci/devices/<dev>/ccissX/cXdY/rev
15 What: /sys/bus/pci/devices/<dev>/ccissX/cXdY/unique_id
22 What: /sys/bus/pci/devices/<dev>/ccissX/cXdY/vendor
29 What: /sys/bus/pci/devices/<dev>/ccissX/cXdY/block:cciss!cXdY
35 What: /sys/bus/pci/devices/<dev>/ccissX/rescan
42 What: /sys/bus/pci/devices/<dev>/ccissX/cXdY/lunid
46 Description: Displays the 8-byte LUN ID used to address logical
49 What: /sys/bus/pci/devices/<dev>/ccissX/cXdY/raid_level
56 What: /sys/bus/pci/devices/<dev>/ccissX/cXdY/usage_count
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| /Documentation/misc-devices/ |
| D | ad525x_dpot.txt | 1 ---------------------------------
3 ---------------------------------
5 The ad525x_dpot driver exports a simple sysfs interface. This allows you to
11 ---------
13 ---------
22 The tolerance files are the read-only factory programmed tolerance settings
23 and may vary greatly on a part-by-part basis. For exact interpretation of
27 -----------
29 -----------
34 # ls /sys/bus/i2c/devices/
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| /Documentation/devicetree/bindings/arm/bcm/ |
| D | brcm,brcmstb.txt | 2 -----------------------------------------------
3 Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
7 - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
11 #address-cells = <2>;
12 #size-cells = <2>;
16 Further, syscon nodes that map platform-specific registers used for general
19 - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
20 - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
21 "brcm,brcmstb-cpu-biu-ctrl",
23 - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
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| /Documentation/devicetree/bindings/mips/ |
| D | mscc.txt | 7 - compatible: "mscc,ocelot"
19 - compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
20 - reg : Should contain registers location and length
24 compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
33 endianness, CPU bus control, CPU status.
36 - compatible: Should be "mscc,ocelot-cpu-syscon", "syscon"
37 - reg : Should contain registers location and length
41 compatible = "mscc,ocelot-cpu-syscon", "syscon";
52 - compatible: Should be "mscc,ocelot-hsio", "syscon", "simple-mfd"
53 - reg : Should contain registers location and length
[all …]
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-aspeed.txt | 4 - #address-cells : should be 1
5 - #size-cells : should be 0
6 - reg : address offset and range of bus
7 - compatible : should be "aspeed,ast2400-i2c-bus"
8 or "aspeed,ast2500-i2c-bus"
9 - clocks : root clock of bus, should reference the APB
11 - resets : phandle to reset controller with the reset number in
13 - interrupts : interrupt number
16 - bus-frequency : frequency of the bus clock in Hz defaults to 100 kHz when not
18 - multi-master : states that there is another master active on this bus.
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| /Documentation/devicetree/bindings/arm/omap/ |
| D | l4.txt | 3 These bindings describe the OMAP SoCs L4 interconnect bus.
6 - compatible : Should be "ti,omap2-l4" for OMAP2 family l4 core bus
7 Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus
8 Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus
9 Should be "ti,omap4-l4-cfg" for OMAP4 family l4 cfg bus
10 Should be "ti,omap4-l4-per" for OMAP4 family l4 per bus
11 Should be "ti,omap4-l4-wkup" for OMAP4 family l4 wkup bus
12 Should be "ti,omap5-l4-cfg" for OMAP5 family l4 cfg bus
13 Should be "ti,omap5-l4-wkup" for OMAP5 family l4 wkup bus
14 Should be "ti,dra7-l4-cfg" for DRA7 family l4 cfg bus
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| /Documentation/devicetree/bindings/display/panel/ |
| D | boe,hv070wsa-100.txt | 1 BOE HV070WSA-100 7.01" WSVGA TFT LCD panel
4 - compatible: should be "boe,hv070wsa-100"
5 - power-supply: regulator to provide the VCC supply voltage (3.3 volts)
6 - enable-gpios: GPIO pin to enable and disable panel (active high)
8 This binding is compatible with the simple-panel binding, which is specified
9 in simple-panel.txt in this directory.
13 node should describe panel's video bus.
15 [1]: Documentation/devicetree/bindings/media/video-interfaces.txt
20 compatible = "boe,hv070wsa-100";
21 power-supply = <&vcc_3v3_reg>;
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| /Documentation/devicetree/bindings/soc/dove/ |
| D | pmu.txt | 4 - compatible: value should be "marvell,dove-pmu".
5 May also include "simple-bus" if there are child devices, in which
7 - reg: two base addresses and sizes of the PM controller and PMU.
8 - interrupts: single interrupt number for the PMU interrupt
9 - interrupt-controller: must be specified as the PMU itself is an
11 - #interrupt-cells: must be 1.
12 - #reset-cells: must be 1.
13 - domains: sub-node containing domain descriptions
16 - ranges: defines the address mapping for child devices, as per the
18 "simple-bus".
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| /Documentation/driver-api/ |
| D | spi.rst | 5 systems because it is a simple and efficient interface: basically a
7 often in the range of 1-20 MHz), a "Master Out, Slave In" (MOSI) data
12 additional chipselect line is usually active-low (nCS); four signals are
15 The SPI bus facilities listed here provide a generalized interface to
24 hardware, which may be as simple as a set of GPIO pins or as complex as
27 whatever bus they sit on (often the platform bus) and SPI, and expose
33 board-specific initialization code. A :c:type:`struct spi_driver
46 .. kernel-doc:: include/linux/spi/spi.h
49 .. kernel-doc:: drivers/spi/spi.c
52 .. kernel-doc:: drivers/spi/spi.c
|
| /Documentation/devicetree/bindings/pinctrl/ |
| D | brcm,bcm4708-pinmux.txt | 14 - compatible: must be one of:
15 "brcm,bcm4708-pinmux"
16 "brcm,bcm4709-pinmux"
17 "brcm,bcm53012-pinmux"
18 - offset: offset of pin registers in the CRU block
21 - "spi": "spi_grp"
22 - "i2c": "i2c_grp"
23 - "pwm": "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp"
24 - "uart1": "uart1_grp"
27 - "mdio": "mdio_grp"
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| /Documentation/ |
| D | bus-virt-phys-mapping.txt | 11 (see Documentation/DMA-API-HOWTO.txt). They continue
13 must not use them. --davidm 00/12/12
20 The AHA-1542 is a bus-master device, and your patch makes the driver give the
22 (because all bus master devices see the physical memory mappings directly).
26 so-called "bus address".
29 that is, normal RAM--see later about other details):
31 - CPU untranslated. This is the "physical" address. Physical address
32 0 is what the CPU sees when it drives zeroes on the memory bus.
34 - CPU translated address. This is the "virtual" address, and is
38 - bus address. This is the address of memory as seen by OTHER devices,
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| /Documentation/devicetree/bindings/rtc/ |
| D | trivial-rtc.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/rtc/trivial-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 This is a list of trivial RTC devices that have simple device tree
18 - $ref: "rtc.yaml#"
23 # AB-RTCMC-32.768kHz-B5ZE-S3: Real Time Clock/Calendar Module with I2C Interface
24 - abracon,abb5zes3
25 # AB-RTCMC-32.768kHz-EOZ9: Real Time Clock/Calendar Module with I2C Interface
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