1ML-AHB interconnect bindings 2 3These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects 4a Cortex-M subsystem with dedicated memories. 5The MCU SRAM and RETRAM memory parts can be accessed through different addresses 6(see "RAM aliases" in [1]) using different buses (see [2]) : balancing the 7Cortex-M firmware accesses among those ports allows to tune the system 8performance. 9 10[1]: https://www.st.com/resource/en/reference_manual/dm00327659.pdf 11[2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping 12 13Required properties: 14- compatible: should be "simple-bus" 15- dma-ranges: describes memory addresses translation between the local CPU and 16 the remote Cortex-M processor. Each memory region, is declared with 17 3 parameters: 18 - param 1: device base address (Cortex-M processor address) 19 - param 2: physical base address (local CPU address) 20 - param 3: size of the memory region. 21 22The Cortex-M remote processor accessed via the mlahb interconnect is described 23by a child node. 24 25Example: 26mlahb { 27 compatible = "simple-bus"; 28 #address-cells = <1>; 29 #size-cells = <1>; 30 dma-ranges = <0x00000000 0x38000000 0x10000>, 31 <0x10000000 0x10000000 0x60000>, 32 <0x30000000 0x30000000 0x60000>; 33 34 m4_rproc: m4@10000000 { 35 ... 36 }; 37}; 38