D (reference) in projects: arch - OpenGrok search results

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Searched refs:D (Results 1 – 25 of 198) sorted by relevance

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/arch/ia64/lib/
D	copy_page_mck.S	`98 #define D (C + 3) macro 99 #define N (D + 1) 106 .rotr v[2PREFETCH_DIST], n[D-C+1] 143 (p[D]) ld8 t2 = [src0], 38 // M0 144 (p[D]) ld8 t4 = [src1], 38 // M1 146 (p[D]) st8 [dst_pre_l2] = n[D-C], 128 // M3 prefetch dst from L2 150 (p[D]) st8 [dst0] = t1, 8 // M2 151 (p[D]) st8 [dst1] = t3, 8 // M3 153 (p[D]) ld8 t5 = [src0], 8 154 (p[D]) ld8 t7 = [src1], 38 [all …]`
D	memcpy_mck.S	66 #define D (C + 1) macro 67 #define N (D + 1) 223 EX(.ex_handler, (p[D]) ld8 t2 = [src0], 38) // M0 224 EK(.ex_handler, (p[D]) ld8 t4 = [src1], 38) // M1 226 EK(.ex_handler_lcpy, (p[D]) st8 [dst_pre_l2] = n8, 128) // M3 prefetch dst from L2 230 EX(.ex_handler, (p[D]) st8 [dst0] = t1, 8) // M2 231 EK(.ex_handler, (p[D]) st8 [dst1] = t3, 8) // M3 233 EX(.ex_handler, (p[D]) ld8 t5 = [src0], 8) 234 EK(.ex_handler, (p[D]) ld8 t7 = [src1], 38) 235 EX(.ex_handler, (p[D]) st8 [dst0] = t2, 38) [all …]
/arch/x86/crypto/
D	twofish-i586-asm_32.S	`68 push d ## D;\ 70 mov s1(%ebp,%edi,4),d ## D;\ 74 ror $16, b ## D;\ 75 xor s2(%ebp,%edi,4),d ## D;\ 77 ror $16, a ## D;\ 80 xor s3(%ebp,%edi,4),d ## D;\ 84 ror $15, b ## D;\ 85 xor (%ebp,%edi,4), d ## D;\ 89 add d ## D, %esi;\ 90 add %esi, d ## D;\ [all …]`
D	sha1_ssse3_asm.S	`116 mov 12(HASH_PTR), D 127 RR F1,A,B,C,D,E,0 128 RR F1,D,E,A,B,C,2 129 RR F1,B,C,D,E,A,4 130 RR F1,E,A,B,C,D,6 131 RR F1,C,D,E,A,B,8 133 RR F1,A,B,C,D,E,10 134 RR F1,D,E,A,B,C,12 135 RR F1,B,C,D,E,A,14 136 RR F1,E,A,B,C,D,16 [all …]`
D	twofish-x86_64-asm_64.S	`72 ror $16, b ## D;\ 75 ror $16, a ## D;\ 82 ror $15, b ## D;\ 89 xor %r9d, c ## D;\ 90 rol $15, c ## D;\ 92 xor %r8d, d ## D; 103 mov b ## D, %r10d;\ 110 ror $16, b ## D;\ 113 ror $16, a ## D;\ 127 xor %r9d, c ## D;\ [all …]`
/arch/arm/mm/
D	proc-arm925.S	109 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 112 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 166 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 170 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 196 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 199 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 203 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 206 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 241 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 261 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry [all …]
D	proc-arm926.S	69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 72 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 132 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 159 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 162 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 166 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 169 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 204 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 224 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 249 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry [all …]
D	proc-mohawk.S	62 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 64 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 114 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache 138 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 141 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 177 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 197 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 221 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 223 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 225 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry [all …]
D	proc-arm920.S	77 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 80 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 132 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 158 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 193 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 213 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 238 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 240 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 241 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 260 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry [all …]
D	proc-arm922.S	79 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 82 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 160 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 195 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 215 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 240 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 242 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 243 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 262 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry [all …]
D	proc-feroceon.S	91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 94 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 149 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way 177 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 180 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 216 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 237 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 252 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start 253 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top 277 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry [all …]
D	proc-arm1022.S	85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 143 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 213 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 238 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 264 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 266 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 267 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 289 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry [all …]
D	proc-arm946.S	58 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 103 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 107 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 137 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 140 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 144 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 147 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 183 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 204 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 228 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry [all …]
D	cache-v4wb.S	`115 bhs __flush_whole_cache @ flush whole D cache 117 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 118 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 164 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 165 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 189 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 191 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 192 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 209 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry`
D	cache-fa.S	66 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache 88 bhs __flush_whole_cache @ flush whole D cache 92 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 127 1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 149 1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line 172 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry 175 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D entry 176 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 194 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 209 1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry
D	proc-arm1020e.S	85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 144 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 174 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 213 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 238 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 264 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 266 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 267 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 289 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry [all …]
D	proc-arm1026.S	85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 168 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 207 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 232 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 258 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 260 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 261 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 283 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 303 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry [all …]
D	proc-xscale.S	91 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 93 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 95 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 97 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 156 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB 160 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 238 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line 239 mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line 263 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 284 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry [all …]
D	proc-arm1020.S	85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 144 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 176 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 218 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 244 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 272 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 276 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 278 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 300 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry [all …]
D	proc-fa526.S	`58 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 61 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 104 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 106 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache 127 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 137 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 140 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4`
D	proc-sa110.S	`65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 68 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 117 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 138 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 154 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 162 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4 165 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4`
D	proc-sa1100.S	`73 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 76 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 127 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 149 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 165 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 185 mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs 186 mcr p15, 0, ip, c7, c7, 0 @ flush I&D cache 201 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 204 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4`
/arch/powerpc/crypto/
D	sha256-spe-glue.c	181 u32 D[SHA256_DIGEST_SIZE >> 2]; in ppc_spe_sha224_final() local 184 ppc_spe_sha256_final(desc, (u8 *)D); in ppc_spe_sha224_final() 187 dst[0] = D[0]; in ppc_spe_sha224_final() 188 dst[1] = D[1]; in ppc_spe_sha224_final() 189 dst[2] = D[2]; in ppc_spe_sha224_final() 190 dst[3] = D[3]; in ppc_spe_sha224_final() 191 dst[4] = D[4]; in ppc_spe_sha224_final() 192 dst[5] = D[5]; in ppc_spe_sha224_final() 193 dst[6] = D[6]; in ppc_spe_sha224_final() 196 memzero_explicit(D, SHA256_DIGEST_SIZE); in ppc_spe_sha224_final()
/arch/arc/plat-eznps/
D	entry.S	`28 ; With no cache coherency mechanism D$ need to be used very carefully. 31 ; 2G-3G: We disable D$ by setting this bit. 32 ; 3G-4G: D$ is disabled by architecture. 34 ; Only FMT left as one who can use D$ where each such page got 38 ; First thing we invalidate D$`
/arch/unicore32/mm/
D	Kconfig	`20 bool "Disable D-Cache (D-bit)" 26 bool "Force write through D-cache" 32 bool "Disable D-cache line ops"`

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