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Searched refs:b1 (Results 1 – 25 of 45) sorted by relevance

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/arch/c6x/lib/
Ddivremu.S24 [b1] lmbd .l2 1, B4, B1
25 ||[!b1] b .s2 B3 ; RETURN A
26 ||[!b1] mvk .d2 1, B4
28 ||[!b1] zero .s1 A5
40 || [b1] subc .l1x A4,B4,A4
41 || [b1] add .s2 -1, B1, B1
42 [b1] subc .l1x A4,B4,A4
43 || [b1] add .s2 -1, B1, B1
48 || [b1] subc .l1x A4,B4,A4
49 || [b1] add .s2 -1, B1, B1
[all …]
/arch/arm/include/asm/
Dxor.h26 : "=r" (src), "=r" (b1), "=r" (b2) \
28 __XOR(a1, b1); __XOR(a2, b2);
32 : "=r" (src), "=r" (b1), "=r" (b2), "=r" (b3), "=r" (b4) \
34 __XOR(a1, b1); __XOR(a2, b2); __XOR(a3, b3); __XOR(a4, b4)
54 register unsigned int b1 __asm__("r8"); in xor_arm4regs_2()
75 register unsigned int b1 __asm__("r8"); in xor_arm4regs_3()
95 register unsigned int b1 __asm__("ip"); in xor_arm4regs_4()
114 register unsigned int b1 __asm__("ip"); in xor_arm4regs_5()
/arch/s390/net/
Dbpf_jit_comp.c113 static inline void reg_set_seen(struct bpf_jit *jit, u32 b1) in reg_set_seen() argument
115 u32 r1 = reg2hex[b1]; in reg_set_seen()
121 #define REG_SET_SEEN(b1) \ argument
123 reg_set_seen(jit, b1); \
126 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]] argument
139 #define EMIT2(op, b1, b2) \ argument
141 _EMIT2(op | reg(b1, b2)); \
142 REG_SET_SEEN(b1); \
153 #define EMIT4(op, b1, b2) \ argument
155 _EMIT4(op | reg(b1, b2)); \
[all …]
/arch/arm/nwfpe/
Dsoftfloat-macros339 value formed by concatenating `b0' and `b1'. Addition is modulo 2^128, so
346 bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 *z0Ptr, bits64 *z1Ptr )
350 z1 = a1 + b1;
359 192-bit value formed by concatenating `b0', `b1', and `b2'. Addition is
371 bits64 b1,
383 z1 = a1 + b1;
397 Subtracts the 128-bit value formed by concatenating `b0' and `b1' from the
406 bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 *z0Ptr, bits64 *z1Ptr )
409 *z1Ptr = a1 - b1;
410 *z0Ptr = a0 - b0 - ( a1 < b1 );
[all …]
/arch/arm/crypto/
Daes-neonbs-core.S85 .macro in_bs_ch, b0, b1, b2, b3, b4, b5, b6, b7
86 veor \b2, \b2, \b1
97 veor \b3, \b3, \b1
98 veor \b1, \b1, \b5
101 .macro out_bs_ch, b0, b1, b2, b3, b4, b5, b6, b7
103 veor \b1, \b1, \b4
106 veor \b6, \b6, \b1
107 veor \b1, \b1, \b5
115 .macro inv_in_bs_ch, b6, b1, b2, b4, b7, b0, b3, b5
116 veor \b1, \b1, \b7
[all …]
Dghash-ce-core.S93 .macro __pmull_p64, rd, rn, rm, b1, b2, b3, b4
107 .macro __pmull_p8, rq, ad, bd, b1=t4l, b2=t3l, b3=t4l, b4=t3l argument
109 .ifc \b1, t4l
114 vmull.p8 t4q, \ad, \b1 @ E = A*B1
280 __pmull_\pn XH, XL_H, SHASH_H, s1h, s2h, s3h, s4h @ a1 * b1
283 __pmull_\pn XM, T1_L, SHASH2_\pn @ (a1+a0)(b1+b0)
/arch/x86/net/
Dbpf_jit_comp.c32 #define EMIT1(b1) EMIT(b1, 1) argument
33 #define EMIT2(b1, b2) EMIT((b1) + ((b2) << 8), 2) argument
34 #define EMIT3(b1, b2, b3) EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3) argument
35 #define EMIT4(b1, b2, b3, b4) EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4) argument
37 #define EMIT1_off32(b1, off) \ argument
38 do { EMIT1(b1); EMIT(off, 4); } while (0)
39 #define EMIT2_off32(b1, b2, off) \ argument
40 do { EMIT2(b1, b2); EMIT(off, 4); } while (0)
41 #define EMIT3_off32(b1, b2, b3, off) \ argument
42 do { EMIT3(b1, b2, b3); EMIT(off, 4); } while (0)
[all …]
Dbpf_jit_comp32.c66 #define EMIT1(b1) EMIT(b1, 1) argument
67 #define EMIT2(b1, b2) EMIT((b1) + ((b2) << 8), 2) argument
68 #define EMIT3(b1, b2, b3) EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3) argument
69 #define EMIT4(b1, b2, b3, b4) \ argument
70 EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4)
72 #define EMIT1_off32(b1, off) \ argument
73 do { EMIT1(b1); EMIT(off, 4); } while (0)
74 #define EMIT2_off32(b1, b2, off) \ argument
75 do { EMIT2(b1, b2); EMIT(off, 4); } while (0)
76 #define EMIT3_off32(b1, b2, b3, off) \ argument
[all …]
/arch/arm64/crypto/
Daes-neonbs-core.S25 .macro in_bs_ch, b0, b1, b2, b3, b4, b5, b6, b7
26 eor \b2, \b2, \b1
37 eor \b3, \b3, \b1
38 eor \b1, \b1, \b5
41 .macro out_bs_ch, b0, b1, b2, b3, b4, b5, b6, b7
43 eor \b1, \b1, \b4
46 eor \b6, \b6, \b1
47 eor \b1, \b1, \b5
55 .macro inv_in_bs_ch, b6, b1, b2, b4, b7, b0, b3, b5
56 eor \b1, \b1, \b7
[all …]
/arch/x86/crypto/
Dghash-clmulni-intel_asm.S55 PCLMULQDQ 0x11 SHASH T1 # T1 = a1 * b1
56 PCLMULQDQ 0x00 T3 T2 # T2 = (a1 + a0) * (b1 + b0)
58 pxor T1, T2 # T2 = a0 * b1 + a1 * b0
Dcast5-avx-x86_64-asm_64.S125 #define F_2(a1, b1, a2, b2, op0, op1, op2, op3) \ argument
126 F_head(b1, RX, RGI1, RGI2, op0); \
129 F_tail(b1, RX, RGI1, RGI2, op1, op2, op3); \
135 #define F1_2(a1, b1, a2, b2) \ argument
136 F_2(a1, b1, a2, b2, vpaddd, xorl, subl, addl)
137 #define F2_2(a1, b1, a2, b2) \ argument
138 F_2(a1, b1, a2, b2, vpxor, subl, addl, xorl)
139 #define F3_2(a1, b1, a2, b2) \ argument
140 F_2(a1, b1, a2, b2, vpsubd, addl, xorl, subl)
142 #define subround(a1, b1, a2, b2, f) \ argument
[all …]
Dcast6-avx-x86_64-asm_64.S125 #define F_2(a1, b1, a2, b2, op0, op1, op2, op3) \ argument
126 F_head(b1, RX, RGI1, RGI2, op0); \
129 F_tail(b1, RX, RGI1, RGI2, op1, op2, op3); \
135 #define F1_2(a1, b1, a2, b2) \ argument
136 F_2(a1, b1, a2, b2, vpaddd, xorl, subl, addl)
137 #define F2_2(a1, b1, a2, b2) \ argument
138 F_2(a1, b1, a2, b2, vpxor, subl, addl, xorl)
139 #define F3_2(a1, b1, a2, b2) \ argument
140 F_2(a1, b1, a2, b2, vpsubd, addl, xorl, subl)
Daesni-intel_asm.S520 pxor \HK, \TMP3 # TMP3 = b1+b0
521 PCLMULQDQ 0x11, \HK, \TMP1 # TMP1 = a1*b1
523 PCLMULQDQ 0x00, \TMP3, \TMP2 # TMP2 = (a0+a1)*(b1+b0)
997 PCLMULQDQ 0x11, \TMP5, \TMP4 # TMP4 = a1*b1
1016 PCLMULQDQ 0x00, \TMP5, \TMP6 # TMP6 = (a1+a0)*(b1+b0)
1031 PCLMULQDQ 0x11, \TMP5, \TMP1 # TMP1 = a1 * b1
1044 PCLMULQDQ 0x00, \TMP5, \TMP2 # TMP2 = (a1+a0)*(b1+b0)
1061 PCLMULQDQ 0x11, \TMP5, \TMP1 # TMP1 = a1*b1
1074 PCLMULQDQ 0x00, \TMP5, \TMP2 # TMP2 = (a1+a0)*(b1+b0)
1092 PCLMULQDQ 0x11, \TMP5, \TMP1 # TMP1 = a1*b1
[all …]
Dcamellia-aesni-avx-asm_64.S433 #define byteslice_16x16b(a0, b0, c0, d0, a1, b1, c1, d1, a2, b2, c2, d2, a3, \ argument
438 transpose_4x4(b0, b1, b2, b3, d2, d3); \
452 vpshufb a0, b1, b1; \
470 transpose_4x4(a1, b1, c1, d1, d2, d3); \
475 vmovdqu b1, st1; \
476 transpose_4x4(a2, b2, c2, d2, b0, b1); \
477 transpose_4x4(a3, b3, c3, d3, b0, b1); \
479 vmovdqu st1, b1; \
Dcamellia-aesni-avx2-asm_64.S467 #define byteslice_16x16b_fast(a0, b0, c0, d0, a1, b1, c1, d1, a2, b2, c2, d2, \ argument
472 transpose_4x4(b0, b1, b2, b3, d2, d3); \
486 vpshufb a0, b1, b1; \
504 transpose_4x4(a1, b1, c1, d1, d2, d3); \
509 vmovdqu b1, st1; \
510 transpose_4x4(a2, b2, c2, d2, b0, b1); \
511 transpose_4x4(a3, b3, c3, d3, b0, b1); \
513 vmovdqu st1, b1; \
/arch/ia64/kernel/
Dmodule.c247 uint64_t b0, b1, *b = (uint64_t *) plt->bundle[1]; in plt_target() local
250 b0 = b[0]; b1 = b[1]; in plt_target()
251 off = ( ((b1 & 0x00fffff000000000UL) >> 36) /* imm20b -> bit 0 */ in plt_target()
252 | ((b0 >> 48) << 20) | ((b1 & 0x7fffffUL) << 36) /* imm39 -> bit 20 */ in plt_target()
253 | ((b1 & 0x0800000000000000UL) << 0)); /* i -> bit 59 */ in plt_target()
296 uint64_t b0, b1, *b = (uint64_t *) plt->bundle[0]; in plt_target() local
298 b0 = b[0]; b1 = b[1]; in plt_target()
299 return ( ((b1 & 0x000007f000000000) >> 36) /* imm7b -> bit 0 */ in plt_target()
300 | ((b1 & 0x07fc000000000000) >> 43) /* imm9d -> bit 7 */ in plt_target()
301 | ((b1 & 0x0003e00000000000) >> 29) /* imm5c -> bit 16 */ in plt_target()
[all …]
Dpatch.c47 u64 m0, m1, v0, v1, b0, b1, *b = (u64 *) (insn_addr & -16); in ia64_patch() local
51 b0 = b[0]; b1 = b[1]; in ia64_patch()
61 b[1] = (b1 & ~m1) | (v1 & m1); in ia64_patch()
/arch/xtensa/platforms/iss/include/platform/
Dsimcall.h71 register int b1 asm("a3") = b; in __simc()
78 : "=a" (ret), "=a" (errno), "+r"(a1), "+r"(b1) in __simc()
/arch/arm64/boot/dts/amd/
DMakefile3 amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb \
/arch/alpha/include/asm/
Dbitops.h445 unsigned long b0, b1, ofs, tmp; in sched_find_first_bit() local
448 b1 = b[1]; in sched_find_first_bit()
450 tmp = (b0 ? b0 : b1); in sched_find_first_bit()
/arch/sh/kernel/cpu/sh4/
Dsoftfloat.c90 void add128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr,
92 void sub128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr,
638 void add128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr, in add128() argument
643 z1 = a1 + b1; in add128()
649 sub128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr, in sub128() argument
652 *z1Ptr = a1 - b1; in sub128()
653 *z0Ptr = a0 - b0 - (a1 < b1); in sub128()
658 bits64 b0, b1; in estimateDiv128To64() local
672 b1 = b << 32; in estimateDiv128To64()
673 add128(rem0, rem1, b0, b1, &rem0, &rem1); in estimateDiv128To64()
/arch/powerpc/crypto/
Daes-tab-4k.S36 .long R(de, 6f, 6f, b1), R(91, c5, c5, 54)
76 .long R(79, b1, b1, c8), R(b6, 5b, 5b, ed)
123 .long R(01, 8d, 8d, 8c), R(b1, d5, d5, 64)
172 .long R(de, b1, 5a, 49), R(25, ba, 1b, 67)
186 .long R(b1, 64, 77, e0), R(bb, 6b, ae, 84)
220 .long R(0c, 0a, 67, b1), R(93, 57, e7, 0f)
279 .long R(e1, 1c, e5, ed), R(7a, 47, b1, 3c)
/arch/ia64/include/uapi/asm/
Dptrace.h193 unsigned long b1; member
/arch/c6x/kernel/
Dsignal.c44 COPY(b0); COPY(b1); COPY(b2); COPY(b3); COPY(b5); COPY(b7); COPY(b9); in restore_sigcontext()
109 COPY(b0); COPY(b1); COPY(b2); COPY(b3); COPY(b5); COPY(b7); COPY(b9); in setup_sigcontext()
/arch/c6x/include/uapi/asm/
Dptrace.h134 REG_PAIR(b1, b0);

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